NDS335N

NDS335N Datasheet

NDS335N N-Channel Logic Level Enhancement Mode Field Effect Transistor

Part	Datasheet
NDS335N	NDS335N (pdf)

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July 1996 NDS335N N-Channel Logic Level Enhancement Mode Field Effect Transistor These N -Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMCIA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. A, 20 V. RDS ON = VGS= V RDS ON = VGS= V. Industry standard outline SOT-23 surface mount package using poprietary SuperSOTTM-3 design for superior thermal and electrical capabilities. High density cell design for extremely low RDS ON . Exceptional on-resistance and maximum DC current capability. Absolute Maximum Ratings Symbol Parameter TA = 25°C unless otherwise noted VDSS VGSS ID Drain-Source Voltage Gate-Source Voltage - Continuous Maximum Drain Current - Continuous Note 1a - Pulsed Maximum Power Dissipation Note 1a Note 1b TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Note 1a Thermal Resistance, Junction-to-Case Note 1 1997 Fairchild Semiconductor Corporation NDS335N 20 8 10 -55 to 150 Units V A W °C °C/W °C/W Electrical Characteristics TA = 25°C unless otherwise noted Symbol Parameter Conditions OFF CHARACTERISTICS BVDSS IDSS Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = 250 µA VDS = 16 V, VGS= 0 V IGSSF Gate - Body Leakage, Forward IGSSR ON CHARACTERISTICS Note 2 VGS th Gate Threshold Voltage VGS = 8 V, VDS = 0 V VGS = -8 V, VDS= 0 V VDS = VGS, ID = 250 µA

PDF Datasheet Preview

July 1996

NDS335N N-Channel Logic Level Enhancement Mode Field Effect Transistor

These N -Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMCIA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package.

A, 20 V. RDS ON = VGS= V RDS ON = VGS= V.

Industry standard outline SOT-23 surface mount package using poprietary SuperSOTTM-3 design for superior thermal and electrical capabilities.

High density cell design for extremely low RDS ON .

Exceptional on-resistance and maximum DC current capability.

Absolute Maximum Ratings

Symbol Parameter

TA = 25°C unless otherwise noted

VDSS VGSS ID

Drain-Source Voltage

Gate-Source Voltage - Continuous

Maximum Drain Current - Continuous Note 1a - Pulsed

Maximum Power Dissipation

Note 1a

Note 1b

TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient

Note 1a

Thermal Resistance, Junction-to-Case Note 1
1997 Fairchild Semiconductor Corporation

NDS335N 20 8 10
-55 to 150

Units V A W °C
°C/W °C/W

Electrical Characteristics TA = 25°C unless otherwise noted

Symbol Parameter

Conditions

OFF CHARACTERISTICS

BVDSS IDSS

Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current

VGS = 0 V, ID = 250 µA VDS = 16 V, VGS= 0 V

IGSSF

Gate - Body Leakage, Forward

IGSSR

ON CHARACTERISTICS Note 2

VGS th

Gate Threshold Voltage

VGS = 8 V, VDS = 0 V VGS = -8 V, VDS= 0 V

VDS = VGS, ID = 250 µA

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Datasheet ID: NDS335N 634603