74ABT245CMTC

74ABT245CMTC Datasheet


74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs

Part Datasheet
74ABT245CMTC 74ABT245CMTC 74ABT245CMTC (pdf)
Related Parts Information
74ABT245CMTCX 74ABT245CMTCX 74ABT245CMTCX
74ABT245CSC 74ABT245CSC 74ABT245CSC
74ABT245CMSA 74ABT245CMSA 74ABT245CMSA
74ABT245CMSAX 74ABT245CMSAX 74ABT245CMSAX
74ABT245CSJX 74ABT245CSJX 74ABT245CSJX
74ABT245CSJ 74ABT245CSJ 74ABT245CSJ
74ABT245CSCX 74ABT245CSCX 74ABT245CSCX
74ABT245CPC 74ABT245CPC 74ABT245CPC
PDF Datasheet Preview
74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs
74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs

The ABT245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented applications. Current sinking capability is 64 mA on both the A and B ports. The Transmit/Receive T/R input determines the direction of data flow through the bidirectional transceiver. Transmit active HIGH enables data from A Ports to B Ports Receive active LOW enables data from B Ports to A Ports. The Output Enable input, when HIGH, disables both A and B ports by placing them in a HIGH Z condition.
s Bidirectional non-inverting buffers s A and B output sink capability of 64 mA, source
capability of 32 mA s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and 250 pF
loads s Guaranteed simultaneous switching, noise level and
dynamic threshold performance s Guaranteed latchup protection s High impedance glitch-free bus loading during entire
power up and power down cycle s Non-destructive hot insertion capability s Disable time is less than enable time to avoid bus
contention
Ordering Code:

Order Number Package Number

Package Description
74ABT245CSC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body
74ABT245CSJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74ABT245CMSA

MSA20
20-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide
74ABT245CMTC

MTC20
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74ABT245CPC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names OE T/R

Description Output Enable Input Active LOW Transmit/Receive Input Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs
1999 Fairchild Semiconductor Corporation DS010945
74ABT245

Logic Symbol Logic Diagram

Truth Table

Inputs

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

Output

Bus B Data to Bus A Bus A Data to Bus B HIGH Z State
74ABT245

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Any Output
in the Disabled or

Power-off State
−0.5V to 5.5V
in the HIGH State Current Applied to Output
−0.5V to VCC
in LOW State Max DC Latchup Source Current
twice the rated IOL mA −500 mA

Over Voltage Latchup I/O

Recommended Operating Conditions

Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate

Data Input Enable Input
−40°C to +85°C +4.5V to +5.5V
50 mV/ns 20 mV/ns

Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.

Note 2 Either voltage limit or current limit is sufficient to protect inputs
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Datasheet ID: 74ABT245CMTC 513049