FDC636P

FDC636P Datasheet

FDC636P P-Channel Logic Level Enhancement Mode Field Effect Transistor

Part	Datasheet
FDC636P	FDC636P (pdf)

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May 1998 FDC636P P-Channel Logic Level Enhancement Mode Field Effect Transistor These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as cellular phone and notebook computer power management and other battery powered circuits where high-side switching, and low in-line power loss are needed in a very small outline surface mount package. A, -20 V. RDS ON = VGS = V RDS ON = VGS = V. SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS ON . Exceptional on-resistance and maximum DC current capability. SOT-23 SuperSOTTM-6 SuperSOTTM-8 G D SuperSOT TM -6 pin 1 D SO-8 SOT-223 SOIC-16 Absolute Maximum RatingsTA = 25°C unless otherwise noted Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage Drain Current - Continuous - Pulsed Note 1a Maximum Power Dissipation Note 1a Note 1b TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Note 1a Thermal Resistance, Junction-to-Case Note 1 1998 Fairchild Semiconductor Corporation FDC636P -20 ±8 -11 -55 to 150 78 30 Units V A °C/W °C/W ELECTRICAL CHARACTERISTICS TA = 25°C unless otherwise noted Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS IDSS

PDF Datasheet Preview

May 1998

FDC636P P-Channel Logic Level Enhancement Mode Field Effect Transistor

These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as cellular phone and notebook computer power management and other battery powered circuits where high-side switching, and low in-line power loss are needed in a very small outline surface mount package.

A, -20 V. RDS ON = VGS = V RDS ON = VGS = V.

SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities.

High density cell design for extremely low RDS ON .

Exceptional on-resistance and maximum DC current capability.

SOT-23

SuperSOTTM-6

SuperSOTTM-8

G D SuperSOT TM -6 pin 1 D

SO-8

SOT-223

SOIC-16

Absolute Maximum RatingsTA = 25°C unless otherwise noted Symbol Parameter

VDSS

Drain-Source Voltage

VGSS

Gate-Source Voltage

Drain Current - Continuous
- Pulsed

Note 1a

Maximum Power Dissipation

Note 1a Note 1b

TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient Note 1a

Thermal Resistance, Junction-to-Case

Note 1
1998 Fairchild Semiconductor Corporation

FDC636P -20 ±8 -11
-55 to 150
78 30

Units V A
°C/W °C/W

ELECTRICAL CHARACTERISTICS TA = 25°C unless otherwise noted

Symbol Parameter

Conditions

Min Typ Max Units

OFF CHARACTERISTICS

BVDSS

IDSS

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Datasheet ID: FDC636P 514077