MPC9109 Rev. 2, 08/2005
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MPC9109FA (pdf) |
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Freescale Semiconductor Technical Data Low Voltage 1:18 Clock Distribution Chip MPC9109 The MPC9109 is a 1:18 low voltage clock distribution chip with V or V LVCMOS output capabilities. The device features the capability to select either a differential LVPECL or an LVCMOS compatible input. The 18 outputs are V or V LVCMOS compatible and feature the drive strength to drive 50 series or parallel terminated transmission lines. With output-to-output skews of 200 ps, the MPC9109 is ideal as a clock distribution chip for the most demanding of synchronous systems. The V outputs also make the device ideal for supplying clocks for a high performance Pentium II microprocessor based design. For a higher performance version of the 9109 refer to the MPC940L data sheet. LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP • LVPECL or LVCMOS clock input • V LVCMOS outputs for Pentium II microprocessor support • 200 ps maximum output-to-output skew V output • Maximum output frequency of 250 MHz V core • 32-lead QFP packaging • Dual or single supply device: • Dual VCC supply voltage, V core and V output • Single V VCC supply voltage for V outputs • Single V VCC supply voltage for V I/O Functional Description FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-04 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-04 With a low output impedance in both the HIGH and LOW logic states, the output buffers of the MPC9109 are ideal for driving series terminated transmission lines. With a 20 output impedance the 9109 has the capability of driving two series terminated lines from each output. This gives the device an effective fanout of If a lower output impedance is desired please see the MPC942 data sheet. If better performance is desired please see the MPC940L data sheet. The differential LVPECL inputs of the MPC9109 allow the device to interface directly with a LVPECL fanout buffer like the MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLK_Sel pin will select the LVCMOS level clock input. All inputs of the MPC9109 have internal pullup/pulldown resistor so they can be left open if unused. The MPC9109 is a single or dual supply device. The device power supply offers a high degree of flexibility. The device can operate with a V core and V output, a V core and V outputs as well as a V core and V outputs. The 32lead QFP package was chosen to optimize performance, board space and cost of the device. The 32-lead TQFP has a 7x7mm body size with a conservative mm pin spacing. Pentium II is a trademark of Intel Corporation. Freescale Semiconductor, Inc., All rights reserved. PECL_CLK LVCMOS_CLK LVCMOS_CLK_Sel INTERNAL PULLDOWN Figure Logic Diagram Q0 16 Q11 GND VCCI GNDO Q5 Q4 Q3 VCCO Q2 Q1 Q0 24 23 22 21 20 19 18 17 MPC9109 12345678 VCCO Q12 Q13 Q14 GNDO Q15 Q16 Q17 Table Function Table LVCMOS CLK_Sel 0 1 Input PECL_CLK LVCMOS_CLK Table Power Supply Voltages Supply Pin Voltage Level VCCI VCCO V or V ± 5% V or V ± 5% VCCI VCCO PECL_CLK PECL_CLK |
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