SY100S351FC

SY100S351FC Datasheet

SY100S351 FINAL

Part	Datasheet
SY100S351FC	SY100S351FC (pdf)

PDF Datasheet Preview
HEX D FLIP-FLOP SY100S351 FINAL s Max. toggle frequency of 700MHz s Clock to Q max. of 1200ps s IEE min. of s Industry standard 100K ECL levels s Extended supply voltage option: VEE = to s Voltage and temperature compensation for improved noise immunity s Internal input pull-down resistors s 50% faster than Fairchild 300K s Better than 20% lower power than Fairchild s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC packages BLOCK DIAGRAM CPb CPa The SY100S351 offers six D-type, edge-triggered, master/slave flip-flops with differential outputs, and is designed for use in high-performance ECL systems. The flip-flops are controlled by the signal from the logical OR operation on a pair of common clock signals CPa, CPb . Data enters the master when both CPa and CPb are LOW and transfers to the slave when either CPa or CPb or both go to a logic HIGH. The Master Reset MR input overrides all other inputs and takes the Q outputs to a logic LOW. The inputs on this device have pull-down resistors. PIN CONFIGURATIONS D1 D0 Q0 VEES Q0 Q1 D2 D3 VEE VEES MR CPa CPb 11 10 9 8 7 6 5 Top View PLCC J28-1 19 20 21 22 23 24 25 Q2 VCCA VCC Q3 D4 D5 Q5 VEES Q5 Q4 CPb CPa MR VEE D3 D2 24 23 22 21 20 19 18 D1 17 D0 Q5 3 Q5 4 Q4 5 Top View 16 Q0 Flatpack F24-1 14 Q1 13 Q1 7 8 9 10 11 12 Q3 VCC VCCA Q2 Issue Date July, 1999 Micrel PIN NAMES Pin D0 D5 CPa, CPb MR Q0 Q5 Q0 Q5 VEES VCCA Function Data Inputs Common Clock Inputs Asynchronous Master Reset Input Data Outputs Complementary Data Outputs VEE Substrate VCCO for ECL Outputs SY100S351 TRUTH TABLES Asynchronous Operation 1 Inputs NOTE H = High Voltage Level L = Low Voltage Level X = Don't Care t = Time before CP Positive Transition t+1 = Time after CP Positive Transition u = LOW-to-HIGH Transition Outputs Qn t+1 PRODUCT ORDERING CODE Ordering Code SY100S351FC SY100S351JC SY100S351JCTR Package Type F24-1 J28-1 J28-1 Operating Range Commercial Micrel 24 LEAD CERPACK F24-1 SY100S351 Micrel 28 LEAD PLCC J28-1 SY100S351 MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA TEL + 1 408 980-9191 FAX + 1 408 914-7878 WEB This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. 2000 Micrel Incorporated 7

PDF Datasheet Preview

HEX D FLIP-FLOP

SY100S351 FINAL
s Max. toggle frequency of 700MHz s Clock to Q max. of 1200ps s IEE min. of s Industry standard 100K ECL levels s Extended supply voltage option:

VEE = to s Voltage and temperature compensation for improved
noise immunity s Internal input pull-down resistors s 50% faster than Fairchild 300K s Better than 20% lower power than Fairchild s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC
packages

BLOCK DIAGRAM

CPb CPa

The SY100S351 offers six D-type, edge-triggered, master/slave flip-flops with differential outputs, and is designed for use in high-performance ECL systems. The flip-flops are controlled by the signal from the logical OR operation on a pair of common clock signals CPa, CPb . Data enters the master when both CPa and CPb are LOW and transfers to the slave when either CPa or CPb or both go to a logic HIGH. The Master Reset MR input overrides all other inputs and takes the Q outputs to a logic LOW. The inputs on this device have pull-down resistors.

PIN CONFIGURATIONS

D1 D0 Q0 VEES Q0 Q1

D2 D3 VEE VEES MR CPa CPb
11 10 9 8 7 6 5

Top View

PLCC

J28-1
19 20 21 22 23 24 25

Q2 VCCA VCC Q3

D4 D5 Q5 VEES Q5 Q4 CPb CPa MR VEE D3 D2
24 23 22 21 20 19
18 D1
17 D0

Q5 3 Q5 4 Q4 5

Top View 16 Q0

Flatpack F24-1
14 Q1
13 Q1
7 8 9 10 11 12

Q3 VCC VCCA Q2

Issue Date July, 1999

Micrel

PIN NAMES

Pin D0 D5 CPa, CPb MR Q0 Q5 Q0 Q5 VEES VCCA

Function Data Inputs Common Clock Inputs Asynchronous Master Reset Input Data Outputs Complementary Data Outputs VEE Substrate VCCO for ECL Outputs

SY100S351

TRUTH TABLES

Asynchronous Operation 1

Inputs

NOTE H = High Voltage Level

L = Low Voltage Level X = Don't Care t = Time before CP Positive Transition t+1 = Time after CP Positive Transition u = LOW-to-HIGH Transition

Outputs Qn t+1
PRODUCT ORDERING CODE
Ordering Code

SY100S351FC SY100S351JC SY100S351JCTR

Package Type F24-1 J28-1 J28-1

Operating Range

Commercial

Micrel
24 LEAD CERPACK F24-1

SY100S351

Micrel
28 LEAD PLCC J28-1

SY100S351

MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA TEL + 1 408 980-9191 FAX + 1 408 914-7878 WEB

This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. 2000 Micrel Incorporated 7

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Datasheet ID: SY100S351FC 647932