AT91FR40161-CI

AT91FR40161-CI Datasheet

• 1024K-word 16-bit Flash Memory 2M bytes Single Voltage Read/Write Sector Erase Architecture, Erase Suspend Capability Dual-plane Organization Allows Concurrent Read and Program/Erase Low-power Operation Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection Reset Input for Device Initialization Sector Program Unlock Command 128-bit Protection Register Factory-programmed AT91 Flash Uploader Software

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AT91FR40161-CI	AT91FR40161-CI (pdf)

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• Incorporates the Processor Core High-performance 32-bit RISC Architecture High-density 16-bit Instruction Set Leader in MIPS/Watt Embedded ICE In-circuit Emulation • 136 Kbytes of On-chip SRAM 32-bit Data Bus, Single Clock Cycle Access • 1024K-word 16-bit Flash Memory 2M bytes Single Voltage Read/Write Sector Erase Architecture, Erase Suspend Capability Dual-plane Organization Allows Concurrent Read and Program/Erase Low-power Operation Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection Reset Input for Device Initialization Sector Program Unlock Command 128-bit Protection Register Factory-programmed AT91 Flash Uploader Software • Fully Programmable External Bus Interface EBI Up to Eight Chip Selects, Maximum External Address Space of 64M Bytes Software Programmable 8/16-bit External Data Bus • 8-level Priority, Individually Maskable, Vectored Interrupt Controller Four External Interrupts, Including a High-priority Low-latency Interrupt Request • 32 Programmable I/O Lines • 3-channel 16-bit Timer/Counter Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel • Two USARTs Two Dedicated Peripheral Data Controller PDC Channels per USART • Programmable Watchdog Timer • Advanced Power-saving Features CPU and Peripherals Can be De-activated Individually • Fully Static Operation 0 Hz to 33 MHz Internal Frequency Range at 3.0V, 85°C • 2.7V to 3.6V Operating Range • -40°C to 85°C Temperature Range • Available in a 120-ball BGA Package AT91 Microcontrollers AT91FR40161 The AT91FR40161 is a member of the Atmel AT91 16/32-bit Microcontroller family, which is based on the ARM7TDMI processor core. The processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. A large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The eight-level priority-vectored interrupt controller, together with the Peripheral Data Controller, significantly enhance real-time device performance. By combining a microcontroller featuring more than 1 Mbit of on-chip SRAM and a wide range of peripheral functions with 16 Mbits of Flash memory in a single compact 120-ball BGA package, the AT91FR40161 provides a powerful, flexible and cost-effective solution to many compute-intensive embedded control applications and offers significant board size and system cost reductions. The Flash memory may be programmed via the JTAG/ICE interface or the factory-programmed Flash Uploader using a single device supply, making the AT91FR40161 ideal for in-system programmable applications. Note This is a summary document. A complete document is not available at this time. For more complete product information, refer to the documents listed in Table 2 on page 8 of this document and contact an Atmel sales office.. Pin Configuration Figure AT91FR40161 Pinout Top View P26 NCS0 NCS2 MCKI MCKO P22 RXD1 P21/TXD1 NTRI P27 NCS1 NWAIT TDI NCS3 VDD GND VDD SCK1 P24 NWODVF NWR1 P13 NUB SCK0 RXD0 VDD P23 NRST FIQ IRQ2 TXD0 P10 IRQ1 P9 IRQ0 P8 TIOB2 GND P30/A22 CS5 TCLK2 TIOB1 TIOA2 GND P29/A21 P31/A23 CS6 CS4 TCLK0 TIOA1 TCLK1 GND VDD TIOB0 NCSF NRD NOE Product overview Ordering information Packaging information Soldering profile Detailed description of Flash memory Document Title ARM7TDMI Thumb Datasheet, lit. no. 0673 AT91x40 Series Datasheet, lit. no. 1354 AT91R40807 Electrical Characteristics Datasheet, lit. no. 1367 AT49BV/LV1604A/1614A T 2-Mbyte 1M x 16/2M x 8 3-volt Only Flash Memory Datasheet AT91FR40161 Summary Datasheet this document AT49BV/LV1604A/1614A T 2-Mbyte 1M x 16/2M x 8 3-volt Only Flash Memory Datasheet 8 AT94FR40161 AT94FR40161 Product Overview Power Supply Input/Output Considerations Master Clock Reset NRST Pin Watchdog Reset Emulation Functions Tri-state Mode JTAG/ICE Debug The AT91FR40161 has a single power supply pin, VDD. The VDD pin supplies the I/O pads and the core. The supported voltage range on VDD is 2.7V to 3.6V. The AT91FR40161 I/O pads accept voltage levels up to the power supply limit. After reset, the microcontroller peripheral I/Os are initialized as inputs to provide the user with maximum flexibility. It is recommended that in any application phase, the inputs to the microcontroller be held at valid logic levels to minimize the power consumption. The AT91FR40161 has a fully static design and works on the Master Clock MCK , provided on the MCKI pin from an external source. The Master Clock is also provided as an output of the device on the pin MCKO, which is multiplexed with a general purpose I/O line. While NRST is active, and after the reset, the MCKO is valid and outputs an image of the MCK signal. The PIO Controller must be programmed to use this pin as standard I/O line. Reset restores the default states of the user interface registers defined in the user interface of each peripheral , and forces the ARM7TDMI to perform the next instruction fetch from address zero. Except for the program counter, the ARM7TDMI registers do not have defined reset states. NRST is active low-level input. It is asserted asynchronously, but exit from reset is synchronized internally to the MCK. The signal presented on MCKI must be active within the specification for a minimum of 10 clock cycles up to the rising edge of NRST to ensure correct operation. The first processor fetch occurs 80 clock cycles after the rising edge of NRST. The watchdog can be programmed to generate an internal reset. In this case, the reset has the same effect as the NRST pin assertion, but the pins BMS and NTRI are not sampled. Boot Mode and Tri-state Mode are not updated. If the NRST pin is asserted and the watchdog triggers the internal reset, the NRST pin has priority. The AT91FR40161 microcontroller provides a tri-state mode, which is used for debug purposes. This enables the connection of an emulator probe to an application board without having to desolder the device from the target board. In tri-state mode, all the output pin drivers of the AT91R40807 microcontroller are disabled. In Tri-state Mode, direct access to the Flash via external pins is provided. This enables production Flash programming using standard Flash programmers prior to board mounting. To enter tri-state mode, the NTRI pin must be held low during the last ten clock cycles before the rising edge of NRST. For normal operation, the NTRI pin must be held high during reset by a resistor of up to 400 NTRI is multiplexed with I/O line P21 and USART1 serial data transmit line TXD1. ARM standard embedded In-circuit Emulation is supported via the JTAG/ICE port. The pins TDI, TDO, TCK and TMS are dedicated to this debug function and can be connected to a host computer via the external ICE interface. In ICE Debug Mode, the Memory Controller Internal Memories Boot Mode Select ARM7TDMI core responds with a non-JTAG chip ID that identifies the microcontroller. This is not fully IEEE1149.1 compliant. The ARM7TDMI processor address space is 4 Gbytes. The memory controller decodes the internal 32-bit address bus and defines three address spaces • Internal memories in the four lowest megabytes • Middle space reserved for the external devices memory or peripherals controlled by the EBI • Internal peripherals in the four highest megabytes In any of these address spaces, the ARM7TDMI operates in little-endian mode only. The AT91FR40161 microcontroller integrates 8 Kbytes of primary internal SRAM that is 32 bits wide and single clock cycle accessible. This memory bank is mapped at address 0x0 after the remap command , allowing ARM7TDMI exception vectors between 0x0 and 0x20 to be modified by the software. The rest of the bank can be used for stack allocation to speed up context saving and restoring , or as data and program storage for critical algorithms. Byte 8-bit , half-word 16-bit or word 32-bit accesses are supported and are executed within one cycle. Fetching Thumb or ARM instructions is supported and internal memory can store twice as many Thumb instructions as ARM ones. The AT91FR40161 also integrates an extended memory bank of 128 Kbytes at address 0x0010 Placing the SRAM on-chip and using the 32-bit data bus bandwidth maximizes the microcontroller performance and minimizes the system power consumption. The 32-bit bus increases the effectiveness of the use of the ARM instruction set, and the ability of processing data that is wider than 16-bit, thus making optimal use of the ARM7TDMI advanced performance. Being able to dynamically update application software in the 128 Kbyte SRAM adds an extra dimension to the AT91FR40161. In order to prevent accidental write to the extended SRAM while the application is running, a write detection feature has been implemented. The AT91FR40161 also integrates a 2 Mbyte Flash memory that is accessed via the External Bus Interface. All data, address and control lines, except for the Chip Select signal, are connected within the device. The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI executes the instruction stored at this address. This means that this address must be mapped in nonvolatile memory after the reset. The input level on the BMS pin during the last 10 clock cycles before the rising edge of the NRST selects the type of boot memory see Table If the embedded Flash memory is to be used as boot memory, the BMS input must be pulled down externally and NCS0 must be connected to NCSF externally. The pin BMS is multiplexed with the I/O line P24 that can be programmed after reset like any standard PIO line. Table Boot Mode Select Ordering Information Table Ordering Information Ordering Code AT91FR40161-CI Package BGA 120 Temperature Operating Range Industrial -40°C to 85°C 18 AT94FR40161 Packaging Information Figure 120-ball Grid Array Package Drawing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A B C D E TOP VIEW F G H J K AT94FR40161 −+ −+ −+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 K J H G F BOTTOM VIEW E D C B A SIDE VIEW −+ −+ −+ All dimensions in mm Table Thermal Resistance Data Parameter Junction-to-ambient thermal resistance Junction-to-case thermal resistance Condition Still Air Table Device and 120-ball BGA Package Maximum Weight Package 120-ball BGA 120-ball BGA Typical 11 Units °C/W Table 120-ball BGA Package Characterisicst Ball diameter Ball land Solder mask opening Plating material Solder ball material Moisture Sensitivity Level mm ± mm ± mm Copper Sn/Pb 4 20 AT94FR40161 Soldering Profile AT94FR40161 Table 8 gives the recommended soldering profile from J-STD-20. Table Soldering Profile Average Ramp-up Rate 183°C to Peak Preheat Temperature 125°C ±25°C Temperature Maintained Above 183°C Time within 5°C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25°C to Peak Temperature Convection or IR/Convection 3°C/sec. max. 120 sec. max 60 sec. to 150 sec. 10 sec. to 20 sec. 220 +5/-0°C or 235 +5/-0°C 6°C/sec. 6 min. max VPR 10°C/sec. 60 sec. 215 to 219°C or 235 +5/-0°C 10°C/sec. Small packages may be subject to higher temperatures if they are reflowed in boards with larger components. In this case, small packages may have to withstand temperatures of up to 235°C, not 220°C IR reflow .

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• Incorporates the Processor Core High-performance 32-bit RISC Architecture High-density 16-bit Instruction Set Leader in MIPS/Watt Embedded ICE In-circuit Emulation
• 136 Kbytes of On-chip SRAM 32-bit Data Bus, Single Clock Cycle Access
• 1024K-word 16-bit Flash Memory 2M bytes Single Voltage Read/Write Sector Erase Architecture, Erase Suspend Capability Dual-plane Organization Allows Concurrent Read and Program/Erase Low-power Operation Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection Reset Input for Device Initialization Sector Program Unlock Command 128-bit Protection Register Factory-programmed AT91 Flash Uploader Software
• Fully Programmable External Bus Interface EBI Up to Eight Chip Selects, Maximum External Address Space of 64M Bytes Software Programmable 8/16-bit External Data Bus
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller Four External Interrupts, Including a High-priority Low-latency Interrupt Request
• 32 Programmable I/O Lines
• 3-channel 16-bit Timer/Counter

Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
• Two USARTs

Two Dedicated Peripheral Data Controller PDC Channels per USART
• Programmable Watchdog Timer
• Advanced Power-saving Features

CPU and Peripherals Can be De-activated Individually
• Fully Static Operation 0 Hz to 33 MHz Internal Frequency Range at 3.0V, 85°C
• 2.7V to 3.6V Operating Range
• -40°C to 85°C Temperature Range
• Available in a 120-ball BGA Package

AT91 Microcontrollers

AT91FR40161

The AT91FR40161 is a member of the Atmel AT91 16/32-bit Microcontroller family, which is based on the ARM7TDMI processor core. The processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. A large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The eight-level priority-vectored interrupt controller, together with the Peripheral Data Controller, significantly enhance real-time device performance.

By combining a microcontroller featuring more than 1 Mbit of on-chip SRAM and a wide range of peripheral functions with 16 Mbits of Flash memory in a single compact 120-ball BGA package, the AT91FR40161 provides a powerful, flexible and cost-effective solution to many compute-intensive embedded control applications and offers significant board size and system cost reductions.

The Flash memory may be programmed via the JTAG/ICE interface or the factory-programmed Flash Uploader using a single device supply, making the AT91FR40161 ideal for in-system programmable applications.

Note This is a summary document. A complete document is not available at this time. For more complete product information, refer to the documents listed in Table 2 on page 8 of this document and contact an Atmel sales office..

Pin Configuration

Figure AT91FR40161 Pinout Top View

P26 NCS0 NCS2

MCKI

MCKO

P22 RXD1

P21/TXD1 NTRI

P27 NCS1 NWAIT TDI NCS3

VDD GND VDD

SCK1

P24 NWODVF NWR1 P13

NUB SCK0

RXD0

VDD P23 NRST

FIQ IRQ2 TXD0

P10 IRQ1

P9 IRQ0

P8 TIOB2

GND P30/A22 CS5

TCLK2 TIOB1 TIOA2

GND P29/A21 P31/A23 CS6 CS4

TCLK0 TIOA1 TCLK1

GND VDD

TIOB0

NCSF

NRD NOE
Product overview Ordering information Packaging information Soldering profile

Detailed description of Flash memory

Document Title ARM7TDMI Thumb Datasheet, lit. no. 0673

AT91x40 Series Datasheet, lit. no. 1354 AT91R40807 Electrical Characteristics Datasheet, lit. no. 1367 AT49BV/LV1604A/1614A T 2-Mbyte 1M x 16/2M x 8 3-volt Only Flash Memory Datasheet

AT91FR40161 Summary Datasheet this document

AT49BV/LV1604A/1614A T 2-Mbyte 1M x 16/2M x 8 3-volt Only Flash Memory Datasheet
8 AT94FR40161

AT94FR40161

Product Overview

Power Supply Input/Output Considerations Master Clock

Reset

NRST Pin Watchdog Reset

Emulation Functions

Tri-state Mode

JTAG/ICE Debug

The AT91FR40161 has a single power supply pin, VDD. The VDD pin supplies the I/O pads and the core. The supported voltage range on VDD is 2.7V to 3.6V.

The AT91FR40161 I/O pads accept voltage levels up to the power supply limit. After reset, the microcontroller peripheral I/Os are initialized as inputs to provide the user with maximum flexibility. It is recommended that in any application phase, the inputs to the microcontroller be held at valid logic levels to minimize the power consumption.

The AT91FR40161 has a fully static design and works on the Master Clock MCK , provided on the MCKI pin from an external source.

The Master Clock is also provided as an output of the device on the pin MCKO, which is multiplexed with a general purpose I/O line. While NRST is active, and after the reset, the MCKO is valid and outputs an image of the MCK signal. The PIO Controller must be programmed to use this pin as standard I/O line.

Reset restores the default states of the user interface registers defined in the user interface of each peripheral , and forces the ARM7TDMI to perform the next instruction fetch from address zero. Except for the program counter, the ARM7TDMI registers do not have defined reset states.

NRST is active low-level input. It is asserted asynchronously, but exit from reset is synchronized internally to the MCK. The signal presented on MCKI must be active within the specification for a minimum of 10 clock cycles up to the rising edge of NRST to ensure correct operation. The first processor fetch occurs 80 clock cycles after the rising edge of NRST.

The watchdog can be programmed to generate an internal reset. In this case, the reset has the same effect as the NRST pin assertion, but the pins BMS and NTRI are not sampled. Boot Mode and Tri-state Mode are not updated. If the NRST pin is asserted and the watchdog triggers the internal reset, the NRST pin has priority.

The AT91FR40161 microcontroller provides a tri-state mode, which is used for debug purposes. This enables the connection of an emulator probe to an application board without having to desolder the device from the target board. In tri-state mode, all the output pin drivers of the AT91R40807 microcontroller are disabled.

In Tri-state Mode, direct access to the Flash via external pins is provided. This enables production Flash programming using standard Flash programmers prior to board mounting.

To enter tri-state mode, the NTRI pin must be held low during the last ten clock cycles before the rising edge of NRST. For normal operation, the NTRI pin must be held high during reset by a resistor of up to 400 NTRI is multiplexed with I/O line P21 and USART1 serial data transmit line TXD1.

ARM standard embedded In-circuit Emulation is supported via the JTAG/ICE port. The pins TDI, TDO, TCK and TMS are dedicated to this debug function and can be connected to a host computer via the external ICE interface. In ICE Debug Mode, the

Memory Controller

Internal Memories

Boot Mode Select

ARM7TDMI core responds with a non-JTAG chip ID that identifies the microcontroller. This is not fully IEEE1149.1 compliant.

The ARM7TDMI processor address space is 4 Gbytes. The memory controller decodes the internal 32-bit address bus and defines three address spaces
• Internal memories in the four lowest megabytes
• Middle space reserved for the external devices memory or peripherals controlled
by the EBI
• Internal peripherals in the four highest megabytes

In any of these address spaces, the ARM7TDMI operates in little-endian mode only.

The AT91FR40161 microcontroller integrates 8 Kbytes of primary internal SRAM that is 32 bits wide and single clock cycle accessible. This memory bank is mapped at address 0x0 after the remap command , allowing ARM7TDMI exception vectors between 0x0 and 0x20 to be modified by the software. The rest of the bank can be used for stack allocation to speed up context saving and restoring , or as data and program storage for critical algorithms. Byte 8-bit , half-word 16-bit or word 32-bit accesses are supported and are executed within one cycle. Fetching Thumb or ARM instructions is supported and internal memory can store twice as many Thumb instructions as ARM ones.

The AT91FR40161 also integrates an extended memory bank of 128 Kbytes at address 0x0010 Placing the SRAM on-chip and using the 32-bit data bus bandwidth maximizes the microcontroller performance and minimizes the system power consumption. The 32-bit bus increases the effectiveness of the use of the ARM instruction set, and the ability of processing data that is wider than 16-bit, thus making optimal use of the ARM7TDMI advanced performance.

Being able to dynamically update application software in the 128 Kbyte SRAM adds an extra dimension to the AT91FR40161. In order to prevent accidental write to the extended SRAM while the application is running, a write detection feature has been implemented.

The AT91FR40161 also integrates a 2 Mbyte Flash memory that is accessed via the External Bus Interface. All data, address and control lines, except for the Chip Select signal, are connected within the device.

The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI executes the instruction stored at this address. This means that this address must be mapped in nonvolatile memory after the reset. The input level on the BMS pin during the last 10 clock cycles before the rising edge of the NRST selects the type of boot memory see Table

If the embedded Flash memory is to be used as boot memory, the BMS input must be pulled down externally and NCS0 must be connected to NCSF externally.

The pin BMS is multiplexed with the I/O line P24 that can be programmed after reset like any standard PIO line.

Table Boot Mode Select
Ordering Information
Table Ordering Information Ordering Code AT91FR40161-CI

Package BGA 120

Temperature Operating Range

Industrial -40°C to 85°C
18 AT94FR40161

Packaging Information

Figure 120-ball Grid Array Package Drawing
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A B C D E TOP VIEW F G H J K

AT94FR40161
−+ −+
−+
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

K J H G F BOTTOM VIEW E D C B A

SIDE VIEW
−+ −+ −+

All dimensions in mm

Table Thermal Resistance Data

Parameter

Junction-to-ambient thermal resistance

Junction-to-case thermal resistance

Condition Still Air

Table Device and 120-ball BGA Package Maximum Weight

Package 120-ball BGA 120-ball BGA

Typical 11

Units °C/W

Table 120-ball BGA Package Characterisicst Ball diameter Ball land Solder mask opening Plating material Solder ball material Moisture Sensitivity Level
mm ± mm ± mm Copper Sn/Pb 4
20 AT94FR40161

Soldering Profile

AT94FR40161

Table 8 gives the recommended soldering profile from J-STD-20.

Table Soldering Profile

Average Ramp-up Rate 183°C to Peak Preheat Temperature 125°C ±25°C Temperature Maintained Above 183°C Time within 5°C of Actual Peak Temperature Peak Temperature Range

Ramp-down Rate Time 25°C to Peak Temperature

Convection or IR/Convection 3°C/sec. max. 120 sec. max
60 sec. to 150 sec.
10 sec. to 20 sec. 220 +5/-0°C or 235 +5/-0°C 6°C/sec. 6 min. max

VPR 10°C/sec.
60 sec. 215 to 219°C or 235 +5/-0°C 10°C/sec.

Small packages may be subject to higher temperatures if they are reflowed in boards with larger components. In this case, small packages may have to withstand temperatures of up to 235°C, not 220°C IR reflow .

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AT91FR40161-CI Datasheet file may be downloaded here without warranties.

Datasheet ID: AT91FR40161-CI 519112