AT49F512-55VI

AT49F512-55VI Datasheet


The AT49F512 is a 5-volt-only in-system programmable and erasable Flash memory. Its 512K of memory is organized as 65,536 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 55 ns with a power dissipation of just 165 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 µA.

Part Datasheet
AT49F512-55VI AT49F512-55VI AT49F512-55VI (pdf)
Related Parts Information
AT49F512-55TI AT49F512-55TI AT49F512-55TI
AT49F512-70TU AT49F512-70TU AT49F512-70TU
AT49F512-55VU AT49F512-55VU AT49F512-55VU
AT49F512-55JU AT49F512-55JU AT49F512-55JU
AT49F512-70VU AT49F512-70VU AT49F512-70VU
PDF Datasheet Preview
• Single Voltage Operation 5V Read 5V Reprogramming
• Fast Read Access Time 55 ns
• Internal Program Control and Timer
• 8K Bytes Boot Block With Lockout
• Fast Erase Cycle Time 10 Seconds
• Byte-by-byte Programming 10 µs/Byte
• Hardware Data Protection
• DATA Polling For End of Program Detection
• Low Power Dissipation
30 mA Active Current 100 µA CMOS Standby Current
• Typical 10,000 Write Cycles
• Green Pb/Halide-free Packaging Option

The AT49F512 is a 5-volt-only in-system programmable and erasable Flash memory. Its 512K of memory is organized as 65,536 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 55 ns with a power dissipation of just 165 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 µA.

To allow for simple in-system reprogrammability, the AT49F512 does not require high input voltages for programming. Five-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49F512 is performed by erasing the entire 512K of memory and then programming on a byte-by-byte basis. The typical byte programming time is a fast 10 µs. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.

The optional 8K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.
512K 64K x 8 5-volt Only Flash Memory

AT49F512

Pin Configurations

Pin Name A0 - A15 CE OE WE I/O0 - I/O7 NC
32-lead PLCC Top View

Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect
4 A12 3 A15 2 NC 1 NC 32 VCC 31 WE 30 NC

A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13
29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7

I/O1 14 I/O2 15 GND 16 I/O3 17 I/O4 18 I/O5 19 I/O6 20
32-lead VSOP Top View 8 x 14 mm or 32-lead TSOP Type 1 Top View 8 x 20 mm

A11 1 A9 2 A8 3

A13 4 A14 5 NC 6 WE 7 VCC 8 NC 9 NC 10 A15 11 A12 12

A7 13 A6 14 A5 15 A4 16
32 OE 31 A10 30 CE 29 I/O7 28 I/O6 27 I/O5 26 I/O4 25 I/O3 24 GND 23 I/O2 22 I/O1 21 I/O0 20 A0 19 A1 18 A2 17 A3
2 AT49F512

Block Diagram

AT49F512

FFFFH
2000H 1FFFH
0000H

Device Operation

Read

The AT49F512 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.

Erasure

Before a byte can be reprogrammed, the 64K bytes memory array or 56K bytes if the boot block featured is used must be erased. The erased state of the memory bits is a logical The entire device can be erased at one time by using a 6-byte software code. The chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern please refer to the Chip Erase Cycle Waveforms .

After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is tEC. If the boot block lockout feature has been enabled, the data in the boot sector will not be erased.

Byte Programming

Once the memory array is erased, the device is programmed to a logical “0” on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to a “1” only erase operations can convert “0”s to “1”s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation please refer to the Command Definitions table . The device will automatically generate the required internal program pulses.

The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified tBP cycle time. The DATA polling feature may also be used to indicate the end of a program cycle.

Boot Block Programming Lockout

The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 8K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated the boot block’s usage as a write protected region is optional to the user. The address range of the boot block is 0000H to 1FFFH.

Once the feature is enabled, the data in the boot block can no longer be erased or programmed. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table.

Boot Block Lockout Detection A software method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode see Software Product Identification Entry and Exit sections a read from address location 00002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification code should be used to return to standard operation.

Product Identification
Ordering Information

AT49F512

Standard Package
tACC

ICC mA

Active

Standby
Ordering Code

Package

Operation Range

AT49F512-55JI

AT49F512-55TI

AT49F512-55VI

Industrial -40° to 85°C

Note:
The AT49F512 has as optional boot block feature. The part number shown in the Ordering Information table is for devices with the boot block in the lower address range i.e., 0000H to 1FFFH . Users requiring the boot block to be in the higher address range should contact Atmel.

Green Package Option Pb/Halide-free
tACC

ICC mA

Active

Standby
Ordering Code

AT49F512-55JU

AT49F512-70TU

AT49F512-55VU

AT49F512-70VU

Package 32J 32T 32V

Operation Range Industrial
-40° to 85°C Industrial
-40° to 85°C Industrial
-40° to 85°C Industrial
-40° to 85°C

Package Type
32-lead, Plastic, J-leaded Chip Carrier Package PLCC
32-lead, Thin Small Outline Package TSOP 8 x 20 mm
32-lead, Thin Small Outline Package VSOP 8 x 14 mm

Packaging Information
32J PLCC

PIN NO. 1 IDENTIFIER
e D1 D

B1 E2

A2 A1 A
0.51 0.020 MAX 3X

COMMON DIMENSIONS Unit of Measure = mm

This package conforms to JEDEC reference MS-016, Variation AE. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum.

SYMBOL MIN NOM MAX NOTE

Note 2

Note 2
10/04/01

TITLE 2325 Orchard Parkway 32J, 32-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131
14 AT49F512
32T TSOP

PIN 1

AT49F512
0º ~ 8º c

Pin 1 Identifier

SEATING PLANE

GAGE PLANE

This package conforms to JEDEC reference MO-142, Variation BD. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum.

COMMON DIMENSIONS Unit of Measure = mm
Ordering Information section.

Atmel Corporation
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Regional Headquarters

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Literature Requests

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Datasheet ID: AT49F512-55VI 518703