CY7C4291-10JC

CY7C4291-10JC Datasheet

CY7C4281 CY7C429164K/128K x 9 Deep Sync FIFOs

Part	Datasheet
CY7C4291-10JC	CY7C4291-10JC (pdf)

Related Parts	Information
CY7C4291-10JXC	CY7C4291-10JXC

PDF Datasheet Preview
CY7C4281 CY7C429164K/128K x 9 Deep Sync FIFOs CY7C4281 CY7C4291 64K/128K x 9 Deep Sync FIFOs • High-speed, low-power, first-in first-out FIFO memories • 64K x 9 CY7C4281 • 128K x 9 CY7C4291 • 0.5-micron CMOS for optimum speed/power • High-speed 100-MHz operation 10-ns read/write cycle times • Low power ICC = 40 mA ISB = 2 mA • Fully asynchronous and simultaneous read and write operation • Empty, Full, and programmable Almost Empty and Almost Full status flags • TTL compatible • Output Enable OE pin • Independent read and write enable pins • Center power and ground pins for reduced noise • Supports free-running 50% duty cycle clock inputs • Width Expansion Capability • Pin-compatible density upgrade to CY7C42X1 family • Pin-compatible density upgrade to IDT72201/11/21/31/41/51 Logic Block Diagram • Pb-Free Packages Available Functional Description The CY7C4281/91 are high-speed, low-power FIFO memories with clocked read and write interfaces. All are nine bits wide. The CY7C4281/91 are pin-compatible to the CY7C42X1 Synchronous FIFO family. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have nine-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock WCLK and two write-enable pins WEN1, WEN2/LD . When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1, WEN2/LD is held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a free-running read clock RCLK and two read enable pins REN1, REN2 . In addition, the CY7C4281/91 has an output enable pin OE . The read RCLK and write WCLK clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data. Pin Configuration INPUT REGISTER PLCC Top View WCLK WEN1 WEN2/LD WRITE CONTROL WRITE POINTER Dual Port RAMARRAY 64K x 9 128K x 9 FLAG PROGRAM REGISTER FLAG LOGIC READ POINTER EF PAE PAF FF D1 D0 PAF PAE REN1 RCLK REN2 4 3 2 1 32 31 30 Ordering Information 64K x 9 Deep Sync FIFO Speed ns Ordering Code CY7C4281-10JC CY7C4281-10JI CY7C4281-15JC CY7C4281-25JC 128K x 9 Deep Sync FIFO Speed ns Ordering Code CY7C4291-10JC CY7C4291-10JXC CY7C4291-10JI CY7C4291-15JC CY7C4291-15JXC CY7C4291-25JC Package Name J65 Package Type 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier Operating Range Commercial Industrial Commercial Package Name J65 Package Type 32-Lead Plastic Leaded Chip Carrier 32-Lead Pb-Free Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Pb-Free Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier Operating Range Commercial Industrial Commercial Page 14 of 16 [+] Feedback Package Diagrams 32-Lead Plastic Leaded Chip Carrier J65 32-Lead Pb-Free Plastic Leaded Chip Carrier J65 CY7C4281 CY7C4291 51-85002-*B All product and company names mentioned in this document are the trademarks of their respective holders. Page 15 of 16 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C4281 CY7C4291 Document History Page Document Title CY7C4281, CY7C4291 64K/128K X 9 Deep Sync FIFOs Document Number 38-06007 Orig. of ECN NO. Issue Date Change Description of Change 106468 07/12/01 SZV Change from Spec number 38-00587 to 38-06007 122259 12/26/02 RBI Power up requirements added to Operating Range Information 127854 08/22/03 FSG Removed Preliminary Fixed empty flag timing diagram Switching waveform diagram typo fixed Added CY7C4291-10JXC, CY7C4291-15JXC to ordering information Page 16 of 16 [+] Feedback

PDF Datasheet Preview

CY7C4281 CY7C429164K/128K x 9 Deep Sync FIFOs

CY7C4281 CY7C4291
64K/128K x 9 Deep Sync FIFOs
• High-speed, low-power, first-in first-out FIFO memories
• 64K x 9 CY7C4281
• 128K x 9 CY7C4291
• 0.5-micron CMOS for optimum speed/power
• High-speed 100-MHz operation 10-ns read/write cycle times
• Low power

ICC = 40 mA ISB = 2 mA
• Fully asynchronous and simultaneous read and write operation
• Empty, Full, and programmable Almost Empty and Almost Full status flags
• TTL compatible
• Output Enable OE pin
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Pin-compatible density upgrade to CY7C42X1 family
• Pin-compatible density upgrade to IDT72201/11/21/31/41/51

Logic Block Diagram
• Pb-Free Packages Available

Functional Description

The CY7C4281/91 are high-speed, low-power FIFO memories with clocked read and write interfaces. All are nine bits wide. The CY7C4281/91 are pin-compatible to the CY7C42X1 Synchronous FIFO family. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.

These FIFOs have nine-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock WCLK and two write-enable pins WEN1, WEN2/LD .

When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1, WEN2/LD is held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a free-running read clock RCLK and two read enable pins REN1, REN2 . In addition, the CY7C4281/91 has an output enable pin OE . The read RCLK and write WCLK clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data.

Pin Configuration

INPUT REGISTER

PLCC Top View

WCLK WEN1 WEN2/LD

WRITE CONTROL

WRITE POINTER

Dual Port

RAMARRAY 64K x 9
128K x 9

FLAG PROGRAM REGISTER

FLAG LOGIC

READ POINTER

EF PAE PAF FF

D1 D0 PAF PAE

REN1 RCLK REN2
4 3 2 1 32 31 30
Ordering Information
64K x 9 Deep Sync FIFO

Speed ns
Ordering Code

CY7C4281-10JC

CY7C4281-10JI

CY7C4281-15JC

CY7C4281-25JC
128K x 9 Deep Sync FIFO

Speed ns
Ordering Code

CY7C4291-10JC

CY7C4291-10JXC

CY7C4291-10JI

CY7C4291-15JC

CY7C4291-15JXC

CY7C4291-25JC

Package Name J65

Package Type
32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier

Operating Range

Commercial Industrial Commercial

Package Name J65

Package Type
32-Lead Plastic Leaded Chip Carrier 32-Lead Pb-Free Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier 32-Lead Pb-Free Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier

Operating Range

Commercial Industrial Commercial

Page 14 of 16 [+] Feedback

Package Diagrams
32-Lead Plastic Leaded Chip Carrier J65 32-Lead Pb-Free Plastic Leaded Chip Carrier J65

CY7C4281 CY7C4291
51-85002-*B

All product and company names mentioned in this document are the trademarks of their respective holders.

Page 15 of 16

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback

CY7C4281 CY7C4291

Document History Page

Document Title CY7C4281, CY7C4291 64K/128K X 9 Deep Sync FIFOs Document Number 38-06007

Orig. of ECN NO. Issue Date Change

Description of Change
106468 07/12/01 SZV Change from Spec number 38-00587 to 38-06007
122259 12/26/02

RBI Power up requirements added to Operating Range Information
127854 08/22/03 FSG Removed Preliminary

Fixed empty flag timing diagram

Switching waveform diagram typo fixed
Added CY7C4291-10JXC, CY7C4291-15JXC to ordering information

Page 16 of 16 [+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C4291-10JC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C4291-10JC 508106