RIO-SERI-T42G5-N1

RIO-SERI-T42G5-N1 Datasheet

TX User Interface The TX User Interface generates all the signals necessary to interface to user logic or the Logical and Transport layers of the RapidIO stack. The main function of this block is to indicate that the TX PHY is ready to receive data from the user. It also controls the discard signal tx_rios_discard, which is used to discard a packet being sent to the core.

Part	Datasheet
RIO-SERI-T42G5-N1	RIO-SERI-T42G5-N1 (pdf)

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ispLever TM CORE Serial RapidIO Physical Layer Interface User’s Guide October 2005 ipug26_02.0 Lattice Semiconductor Serial RapidIO Physical Layer Interface User’s Guide Introduction RapidIO is a high performance, low pin count, packet switched, full duplex, system level interconnect architecture. The architecture addresses the need for faster bus speeds in an intra-system interconnect for microprocessors, digital signal processors, communications and network processors. It also offers error management and provides a architecture for recovering from and reporting transmission errors. RapidIO systems contain endpoint and switch processing elements. The RapidIO interconnect architecture is partitioned into a layered hierarchy of which includes Logical, Common Transport and Physical layers. The Logical layer the operations and transactions by which endpoint processing elements communicate with each other. The Common Transport layer how the transactions are routed from one endpoint processing elements to another through switch processing elements. The Physical layer the interface between two devices and the packet transport mechanism, control and electrical characteristics. Currently there are two Physical layer an 8-bit or 16-bit wide parallel and a 1-lane 1x or 4-lane 4x serial This user’s guide explains the information about Lattice’s Serial RapidIO Physical Layer and interface. The Serial RapidIO Physical Layer core comes with the following documentation and • Data sheet • User’s guide • Lattice evaluation gate level netlist • Simulation model for evaluation • Core instantiation template • Testbench and testbench coding template The following experience is recommended for the user to implement a design using this IP: • Familiarity with the Lattice ORT82G5/ORT42G5 FPSC architecture • Familiarity with simulation, synthesis and Lattice design tools • Knowledge of the RapidIO Interconnect Part VI Physical Layer 1x/4x LP-Serial • Supports high speed 1x mode up to Gbps • 8B/10B encoding and decoding • Clock and Data Recovery CDR • Lane synchronization • CRC generation and checking • Error detection • Packet/control symbol assembly and de-assembly • Simple user interface for easy integration into user logic • Targets ORT82G5/ORT42G5 FPSC Lattice Semiconductor Serial RapidIO Physical Layer Interface User’s Guide This Serial RapidIO core is optimized to support ORT82G5/ORT42G5 FPSCs. For more information on Lattice products, refer to the Lattice web site at Block Diagram Figure Physical Layer Block Diagram PMI Interface RX USER Interface RX Transmit Ack Ctrl RX USR I/F Phy Layer Management I/F Control Receive Transmit RX Symbol Decoder TX Ctrl Symb RX Receive Pkt Ack Ctrl RX CRC Checker RX Packet/ Control DisAssy TX Pkt Data SERDES Interface 64 Block RD RD_N RX Serial RapidIO Embedded SERDES on ORT82G5/ORT42G5 The Ordering Part Number OPN for all of this core is RIO-SERI-T42G5-N1. Table 8 lists the netlists available as Evaluation Packages for the ORCA Series 4 FPSC devices, which can be downloaded from the Lattice website at You can use the IPexpress software tool to help generate new of this IP core. IPexpress is the Lattice IP utility, and is included as a standard feature of the ispLEVER design tools. Details regarding the usage of IPexpress can be found in the IPexpress and ispLEVER help system. For more information on the ispLEVER design tools, visit the Lattice web site at

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ispLever TM CORE

Serial RapidIO Physical Layer Interface

User’s Guide

October 2005 ipug26_02.0

Lattice Semiconductor

Serial RapidIO Physical Layer Interface User’s Guide

Introduction

RapidIO is a high performance, low pin count, packet switched, full duplex, system level interconnect architecture. The architecture addresses the need for faster bus speeds in an intra-system interconnect for microprocessors, digital signal processors, communications and network processors. It also offers error management and provides a architecture for recovering from and reporting transmission errors.

RapidIO systems contain endpoint and switch processing elements. The RapidIO interconnect architecture is partitioned into a layered hierarchy of which includes Logical, Common Transport and Physical layers. The Logical layer the operations and transactions by which endpoint processing elements communicate with each other. The Common Transport layer how the transactions are routed from one endpoint processing elements to another through switch processing elements. The Physical layer the interface between two devices and the packet transport mechanism, control and electrical characteristics. Currently there are two Physical layer an 8-bit or 16-bit wide parallel and a 1-lane 1x or 4-lane 4x serial

This user’s guide explains the information about Lattice’s Serial RapidIO Physical Layer and interface.

The Serial RapidIO Physical Layer core comes with the following documentation and
• Data sheet
• User’s guide
• Lattice evaluation gate level netlist
• Simulation model for evaluation
• Core instantiation template
• Testbench and testbench coding template

The following experience is recommended for the user to implement a design using this IP:
• Familiarity with the Lattice ORT82G5/ORT42G5 FPSC architecture
• Familiarity with simulation, synthesis and Lattice design tools
• Knowledge of the RapidIO Interconnect Part VI Physical Layer 1x/4x LP-Serial
• Supports high speed 1x mode up to Gbps
• 8B/10B encoding and decoding
• Clock and Data Recovery CDR
• Lane synchronization
• CRC generation and checking
• Error detection
• Packet/control symbol assembly and de-assembly
• Simple user interface for easy integration into user logic
• Targets ORT82G5/ORT42G5 FPSC

Lattice Semiconductor

Serial RapidIO Physical Layer Interface User’s Guide

This Serial RapidIO core is optimized to support ORT82G5/ORT42G5 FPSCs.

For more information on Lattice products, refer to the Lattice web site at

Block Diagram

Figure Physical Layer Block Diagram

PMI Interface

RX USER Interface

RX Transmit Ack Ctrl

RX USR I/F

Phy Layer Management

I/F Control

Receive Transmit

RX Symbol Decoder

TX Ctrl Symb

RX Receive Pkt Ack

Ctrl

RX CRC Checker

RX Packet/ Control DisAssy

TX Pkt Data

SERDES

Interface
64 Block

RD RD_N

RX Serial RapidIO

Embedded SERDES on ORT82G5/ORT42G5
The Ordering Part Number OPN for all of this core is RIO-SERI-T42G5-N1. Table 8 lists the netlists available as Evaluation Packages for the ORCA Series 4 FPSC devices, which can be downloaded from the Lattice website at

You can use the IPexpress software tool to help generate new of this IP core. IPexpress is the Lattice IP utility, and is included as a standard feature of the ispLEVER design tools. Details regarding the usage of IPexpress can be found in the IPexpress and ispLEVER help system. For more information on the ispLEVER design tools, visit the Lattice web site at

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived RIO-SERI-T42G5-N1 Datasheet file may be downloaded here without warranties.

Datasheet ID: RIO-SERI-T42G5-N1 645501