GAL18V10B-10LJ

GAL18V10B-10LJ Datasheet

Product Line GAL18V10

Part	Datasheet
GAL18V10B-10LJ	GAL18V10B-10LJ (pdf)

Related Parts	Information
GAL18V10B-10LP	GAL18V10B-10LP
GAL18V10B-15LJ	GAL18V10B-15LJ
GAL18V10B-15LP	GAL18V10B-15LP
GAL18V10B-20LJ	GAL18V10B-20LJ
GAL18V10B-20LP	GAL18V10B-20LP

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Device Datasheet September 2010 All Devices Discontinued! Product Change Notifications PCNs have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line GAL18V10 Ordering Part Number GAL18V10B-7LJ GAL18V10B-7LP GAL18V10B-10LJ GAL18V10B-10LP GAL18V10B-15LJ GAL18V10B-15LP GAL18V10B-20LJ GAL18V10B-20LP Product Status Reference PCN#06-07 Discontinued PCN#13-10 5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone 503 268-8000 FAX 503 268-8347 Internet: GAL18V10 High Performance E2CMOS PLD Generic Array Logic Functional Block Diagram • HIGH PERFORMANCE TECHNOLOGY ns Maximum Propagation Delay Fmax = 111 MHz I/CLK RESET ns Maximum from Clock Input to Data Output TTL Compatible 16 mA Outputs 8 OLMC I/O/Q Advanced CMOS Technology • LOW POWER CMOS 75 mA Typical Icc • ACTIVE PULL-UPS ON ALL PINS S • E2 CELL TECHNOLOGY Reconfigurable Logic Reprogrammable Cells E D 100% Tested/100% Yields High Speed Electrical Erasure <100ms 20 Year Data Retention IC E • TEN OUTPUT LOGIC MACROCELLS Uses Standard 22V10 Macrocell Architecture Maximum Flexibility for Complex Logic Designs V U • PRELOAD AND POWER-ON RESET OF REGISTERS 100% Functional Testability • APPLICATIONS INCLUDE: E IN DMAControl State Machine Control High Speed Graphics Processing Standard Logic Speed Upgrade D T • ELECTRONIC SIGNATURE FOR IDENTIFICATION L N The GAL18V10, at ns maximum propagation delay time, com- bines a high performance CMOS process with Electrically Erasable E2 floating gate technology to provide a very flexible 20-pin L O PLD. CMOS circuitry allows the GAL18V10 to consume much less power when compared to its bipolar counterparts. The E2 technology offers high speed <100ms erase times, providing the ability A C to reprogram or reconfigure the device quickly and efficiently. By building on the popular 22V10 architecture, the GAL18V10 eliminates the learning curve usually associated with using a new IS device architecture. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell OLMC to be configured by the user. The GAL18V10 OLMC is fully compatible with the OLMC in standard bipolar and CMOS 22V10 de- D vices. OLMC I/O/Q PROGRAMMABLE AND-ARRAY 96X36 OLMC I/O/Q GAL18V10 Ordering Information Commercial Grade Specifications Tpd ns Tsu ns Tco ns Icc mA Ordering # Package 115 GAL18V10B-7LP1 20-Pin Plastic DIP 115 GAL18V10B-7LJ1 20-Lead PLCC 115 GAL18V10B-10LP 20-Pin Plastic DIP 115 GAL18V10B-10LJ 20-Lead PLCC 115 GAL18V10B-15LP 20-Pin Plastic DIP 115 GAL18V10B-15LJ 20-Lead PLCC 115 GAL18V10B-20LP 20-Pin Plastic DIP S 115 GAL18V10B-20LJ 20-Lead PLCC Discontinued per PCN Contact Rochester Electronics for available inventory. ICE ED Part Number Description _ XX X V U GAL18V10B Device Name E IN Speed ns ADLLISDCONT L=LowPower Power Grade Blank = Commercial Package P = Plastic DIP J = PLCC Specifications GAL18V10 Output Logic Macrocell OLMC The GAL18V10 has a variable number of product terms per OLMC. The GAL18V10 has a product term for Asynchronous Reset AR Of the ten available OLMCs, two OLMCs have access to ten prod- and a product term for Synchronous Preset SP . These two prod- uct terms pins 14 and 15 , and the other eight OLMCs have eight uct terms are common to all registered OLMCs. The Asynchronous product terms each. In addition to the product terms available for Reset sets all registered outputs to zero any time this dedicated logic, each OLMC has an additional product-term dedicated to out- product term is asserted. The Synchronous Preset sets all registers put enable control. to a logic one on the rising edge of the next clock pulse after this product term is asserted. The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active S high or active low. NOTE The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen. ICE D AR E IN SP

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Device Datasheet

September 2010

All Devices Discontinued!

Product Change Notifications PCNs have been issued to discontinue all devices in this data sheet.

The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status.

Product Line GAL18V10
Ordering Part Number GAL18V10B-7LJ GAL18V10B-7LP GAL18V10B-10LJ GAL18V10B-10LP GAL18V10B-15LJ GAL18V10B-15LP GAL18V10B-20LJ GAL18V10B-20LP

Product Status

Reference PCN#06-07

Discontinued

PCN#13-10
5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone 503 268-8000 FAX 503 268-8347 Internet:

GAL18V10

High Performance E2CMOS PLD Generic Array Logic

Functional Block Diagram
• HIGH PERFORMANCE TECHNOLOGY
ns Maximum Propagation Delay

Fmax = 111 MHz

I/CLK

RESET
ns Maximum from Clock Input to Data Output TTL Compatible 16 mA Outputs
8 OLMC

I/O/Q

Advanced CMOS Technology
• LOW POWER CMOS 75 mA Typical Icc
• ACTIVE PULL-UPS ON ALL PINS

S
• E2 CELL TECHNOLOGY Reconfigurable Logic Reprogrammable Cells E D 100% Tested/100% Yields High Speed Electrical Erasure <100ms 20 Year Data Retention

IC E
• TEN OUTPUT LOGIC MACROCELLS Uses Standard 22V10 Macrocell Architecture Maximum Flexibility for Complex Logic Designs

V U
• PRELOAD AND POWER-ON RESET OF REGISTERS 100% Functional Testability
• APPLICATIONS INCLUDE:

E IN DMAControl

State Machine Control High Speed Graphics Processing Standard Logic Speed Upgrade

D T
• ELECTRONIC SIGNATURE FOR IDENTIFICATION

L N The GAL18V10, at ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Erasable E2 floating gate technology to provide a very flexible 20-pin

L O PLD. CMOS circuitry allows the GAL18V10 to consume much less
power when compared to its bipolar counterparts. The E2 technology offers high speed <100ms erase times, providing the ability

A C to reprogram or reconfigure the device quickly and efficiently.

By building on the popular 22V10 architecture, the GAL18V10 eliminates the learning curve usually associated with using a new

IS device architecture. The generic architecture provides maximum
design flexibility by allowing the Output Logic Macrocell OLMC to be configured by the user. The GAL18V10 OLMC is fully compatible with the OLMC in standard bipolar and CMOS 22V10 de-

D vices.

OLMC

I/O/Q

PROGRAMMABLE AND-ARRAY 96X36

OLMC

I/O/Q
GAL18V10 Ordering Information

Commercial Grade Specifications

Tpd ns Tsu ns Tco ns Icc mA
Ordering #

Package
115 GAL18V10B-7LP1
20-Pin Plastic DIP
115 GAL18V10B-7LJ1
20-Lead PLCC
115 GAL18V10B-10LP
20-Pin Plastic DIP
115 GAL18V10B-10LJ
20-Lead PLCC
115 GAL18V10B-15LP
20-Pin Plastic DIP
115 GAL18V10B-15LJ
20-Lead PLCC
115 GAL18V10B-20LP
20-Pin Plastic DIP

S 115 GAL18V10B-20LJ
20-Lead PLCC

Discontinued per PCN Contact Rochester Electronics for available inventory.

ICE ED Part Number Description
_ XX X

V U GAL18V10B Device Name E IN Speed ns

ADLLISDCONT L=LowPower Power

Grade Blank = Commercial

Package P = Plastic DIP J = PLCC

Specifications GAL18V10

Output Logic Macrocell OLMC

The GAL18V10 has a variable number of product terms per OLMC. The GAL18V10 has a product term for Asynchronous Reset AR

Of the ten available OLMCs, two OLMCs have access to ten prod- and a product term for Synchronous Preset SP . These two prod-
uct terms pins 14 and 15 , and the other eight OLMCs have eight uct terms are common to all registered OLMCs. The Asynchronous
product terms each. In addition to the product terms available for Reset sets all registered outputs to zero any time this dedicated
logic, each OLMC has an additional product-term dedicated to out- product term is asserted. The Synchronous Preset sets all registers
put enable control.
to a logic one on the rising edge of the next clock pulse after this
product term is asserted.

The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active

S high or active low.

NOTE The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen.

ICE D AR

E IN SP

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Datasheet ID: GAL18V10B-10LJ 645467