NDT455N

NDT455N Datasheet

NDT455N N-Channel Enhancement Mode Field Effect Transistor

Part	Datasheet
NDT455N	NDT455N (pdf)

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July 1996 NDT455N N-Channel Enhancement Mode Field Effect Transistor These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as DC motor control and DC/DC conversion where fast switching, low in-line power loss, and resistance to transients are needed. A, 30 V. RDS ON = VGS = 10 V RDS ON = VGS = V. High density cell design for extremely low RDS ON . High power and current handling capability in a widely used surface mount package. Absolute Maximum Ratings TA = 25°C unless otherwise noted Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage Drain Current - Continuous - Pulsed Note 1a Maximum Power Dissipation Note 1a Note 1b Note 1c TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case Note 1a Note 1 1997 Fairchild Semiconductor Corporation NDT455N 30 20 ± ± 40 3 -65 to 150 42 12 Units V A °C/W °C/W Electrical Characteristics TA = 25°C unless otherwise noted Symbol Parameter Conditions OFF CHARACTERISTICS BVDSS IDSS Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = 250 µA VDS = 24 V, VGS = 0 V IGSSF Gate - Body Leakage, Forward IGSSR ON CHARACTERISTICS Note 2 VGS th Gate Threshold Voltage VGS = 20 V, VDS = 0 V VGS = -20 V, VDS= 0 V VDS = VGS, ID = 250 µA

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July 1996

NDT455N N-Channel Enhancement Mode Field Effect Transistor

These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as DC motor control and DC/DC conversion where fast switching, low in-line power loss, and resistance to transients are needed.

A, 30 V. RDS ON = VGS = 10 V RDS ON = VGS = V.

High density cell design for extremely low RDS ON . High power and current handling capability in a widely used surface mount package.

Absolute Maximum Ratings TA = 25°C unless otherwise noted

Symbol Parameter

VDSS

Drain-Source Voltage

VGSS

Gate-Source Voltage

Drain Current - Continuous
- Pulsed

Note 1a

Maximum Power Dissipation

Note 1a Note 1b Note 1c

TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case

Note 1a Note 1
1997 Fairchild Semiconductor Corporation

NDT455N 30 20
± ± 40 3
-65 to 150
42 12

Units V A
°C/W °C/W

Electrical Characteristics TA = 25°C unless otherwise noted

Symbol Parameter

Conditions

OFF CHARACTERISTICS

BVDSS IDSS

Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current

VGS = 0 V, ID = 250 µA VDS = 24 V, VGS = 0 V

IGSSF

Gate - Body Leakage, Forward

IGSSR

ON CHARACTERISTICS Note 2

VGS th

Gate Threshold Voltage

VGS = 20 V, VDS = 0 V VGS = -20 V, VDS= 0 V

VDS = VGS, ID = 250 µA

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Datasheet ID: NDT455N 634639