SAF-TC1130-L100EB BB

SAF-TC1130-L100EB BB Datasheet

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Part	Datasheet
SAF-TC1130-L100EB BB	SAF-TC1130-L100EB BB (pdf)

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SAF-TC1130-L150EB BB	SAF-TC1130-L150EB BB

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Data Sheet, V1.0, Feb 2005 TC1130 32-Bit Single-Chip Microcontroller Advance Information Microcontrollers Never stop thinking. Edition 2005-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Data Sheet, V1.0, Feb 2005 TC1130 32-Bit Single-Chip Microcontroller Advance Information Microcontrollers Never stop thinking. 2005-02 Previous Version: none V1.0 Controller Area Network CAN License of Robert Bosch GmbH We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal including a reference to this document to: TC1130 Table of Contents Summary of Features 1 General Device Information 3 Block Diagram 3 Logic Symbol 4 Pin Configuration 5 Pin Definitions and Functions 6 Functional Description 20 On-Chip Memories 20 Address Map 21 Memory Protection System 27 Protection for Direct translation 27 Protection for PTE based translation 28 Memory Checker 28 On-Chip Bus System 29 Local Memory Bus LMB 29 Flexible Peripheral Interconnect Bus FPI 29 LFI 30 LMB External Bus Unit 31 Direct Memory Access DMA 33 Interrupt System 35 Parallel Ports 37 Asynchronous/Synchronous Serial Interface ASC 38 High-Speed Synchronous Serial Interface SSC 41 Inter IC Serial Interface IIC 43 Universal Serial Bus Interface USB 45 MultiCAN 47 Micro Link Serial Bus Interface MLI 50 General Purpose Timer Unit GPTU 52 Capture/Compare Unit 6 CCU6 54 Ethernet Controller 56 System Timer 58 Watchdog Timer 60 System Control Unit 62 Boot Options 63 Power Management System 64 On-Chip Debug Support 65 Clock Generation Unit 67 Power Supply 70 Power Sequencing 71 Identification Register Values 72 Electrical Parameters 74 Data Sheet V1.0, 2005-02 TC1130 Table of Contents buffer control • Provides RMW signal reflecting read-modify-write action • Supports Little Endian byte ordering • Provides signal for controlling data flow of slow-memory buffer Data Sheet V1.0, 2005-02 TC1130 Advance Information Functional Description Direct Memory Access DMA The Direct Memory Access Controller executes DMA transactions from a source address location to a destination address location, without intervention of the CPU. One DMA transaction is controlled by one DMA channel. Each DMA channel has assigned its own channel register set. The total of 8 channels are provided by one DMA sub-block. The DMA module is connected to 3 bus interfaces in TC1130, the Flexible Peripheral Interconnect Bus FPI , the DMA Bus and the Micro Link Bus. It can do transfers on each of the buses as well as between the buses. In addition, it bridges accesses from the Flexible Peripheral Interconnect Bus to the peripherals on the DMA Bus, allowing easy access to these peripherals by CPU. Clock control, address decoding, DMA request wiring, and DMA interrupt service request control are implementation specific and managed outside the DMA controller kernel. Features: • 8 independent DMA channels Up to 8 selectable request inputs per DMA channel Programmable priority of DMA channels within a DMA sub-block 2 levels Software and hardware DMA request generation Hardware requests by selected peripherals and external inputs • Programmable priority of the DMA sub-block on the bus interfaces • Buffer capability for move actions on the buses min. 1 move per bus is buffered . • Individually programmable operation modes for each DMA channel Single mode stops and disables DMA channel after a predefined number of DMA transfers Continuous mode DMA channel remains enabled after a predefined number of DMA transfers DMA transaction can be repeated. Programmable address modification • Full 32-bit addressing capability of each DMA channel 4-Gbyte address range Support of circular buffer addressing mode • Programmable data width of a DMA transaction 8-bit, 16-bit, or 32-bit • Micro Link supported • Register set for each DMA channel Source and destination address register Channel control and status register Transfer count register • Flexible interrupt generation the service request node logic for the MLI channels is also implemented in the DMA module • All buses/interfaces connected to the DMA module must work at the same frequency • Read/write requests of the FPI Bus Side to the Remote Peripherals are bridged to the DMA Bus only the DMA is master on the DMA bus Data Sheet V1.0, 2005-02 TC1130 Advance Information Functional Description The basic structure and external interconnections of the DMA are shown in Figure Clock Control f DMA DMA Controller Address Decoder Arbiter/ Switch Control 4 MultiCAN 2 ASC0 2 ASC1 2 ASC2 SSC0 2 SSC1 1 CCU60 1 CCU61 4 MLI0 4 MLI1 DMA Request Wiring Matrix 1 I2C

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Data Sheet, V1.0, Feb 2005

TC1130
32-Bit Single-Chip Microcontroller Advance Information

Microcontrollers

Never stop thinking.

Edition 2005-02

Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany

Infineon Technologies AG

All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Data Sheet, V1.0, Feb 2005

TC1130
32-Bit Single-Chip Microcontroller Advance Information

Microcontrollers

Never stop thinking.
2005-02

Previous Version:
none

V1.0

Controller Area Network CAN License of Robert Bosch GmbH

We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal including a reference to this document to:

TC1130

Table of Contents

Summary of Features 1

General Device Information 3

Block Diagram 3

Logic Symbol 4

Pin Configuration 5

Pin Definitions and Functions 6

Functional Description 20 On-Chip Memories 20 Address Map 21 Memory Protection System 27

Protection for Direct translation 27 Protection for PTE based translation 28 Memory Checker 28 On-Chip Bus System 29 Local Memory Bus LMB 29 Flexible Peripheral Interconnect Bus FPI 29 LFI 30 LMB External Bus Unit 31 Direct Memory Access DMA 33 Interrupt System 35 Parallel Ports 37 Asynchronous/Synchronous Serial Interface ASC 38 High-Speed Synchronous Serial Interface SSC 41 Inter IC Serial Interface IIC 43 Universal Serial Bus Interface USB 45 MultiCAN 47 Micro Link Serial Bus Interface MLI 50 General Purpose Timer Unit GPTU 52 Capture/Compare Unit 6 CCU6 54 Ethernet Controller 56 System Timer 58 Watchdog Timer 60 System Control Unit 62 Boot Options 63 Power Management System 64 On-Chip Debug Support 65 Clock Generation Unit 67 Power Supply 70 Power Sequencing 71 Identification Register Values 72

Electrical Parameters 74

Data Sheet

V1.0, 2005-02

TC1130

Table of Contents
buffer control
• Provides RMW signal reflecting read-modify-write action
• Supports Little Endian byte ordering
• Provides signal for controlling data flow of slow-memory buffer

Data Sheet

V1.0, 2005-02

TC1130

Advance Information

Functional Description

Direct Memory Access DMA

The Direct Memory Access Controller executes DMA transactions from a source address location to a destination address location, without intervention of the CPU. One DMA transaction is controlled by one DMA channel. Each DMA channel has assigned its own channel register set. The total of 8 channels are provided by one DMA sub-block.

The DMA module is connected to 3 bus interfaces in TC1130, the Flexible Peripheral Interconnect Bus FPI , the DMA Bus and the Micro Link Bus. It can do transfers on each of the buses as well as between the buses.

In addition, it bridges accesses from the Flexible Peripheral Interconnect Bus to the peripherals on the DMA Bus, allowing easy access to these peripherals by CPU. Clock control, address decoding, DMA request wiring, and DMA interrupt service request control are implementation specific and managed outside the DMA controller kernel.

Features:
• 8 independent DMA channels Up to 8 selectable request inputs per DMA channel Programmable priority of DMA channels within a DMA sub-block 2 levels Software and hardware DMA request generation Hardware requests by selected peripherals and external inputs
• Programmable priority of the DMA sub-block on the bus interfaces
• Buffer capability for move actions on the buses min. 1 move per bus is buffered .
• Individually programmable operation modes for each DMA channel

Single mode stops and disables DMA channel after a predefined number of DMA transfers

Continuous mode DMA channel remains enabled after a predefined number of DMA transfers DMA transaction can be repeated.

Programmable address modification
• Full 32-bit addressing capability of each DMA channel
4-Gbyte address range Support of circular buffer addressing mode
• Programmable data width of a DMA transaction 8-bit, 16-bit, or 32-bit
• Micro Link supported
• Register set for each DMA channel Source and destination address register Channel control and status register Transfer count register
• Flexible interrupt generation the service request node logic for the MLI channels is also implemented in the DMA module
• All buses/interfaces connected to the DMA module must work at the same frequency
• Read/write requests of the FPI Bus Side to the Remote Peripherals are bridged to the DMA Bus only the DMA is master on the DMA bus

Data Sheet

V1.0, 2005-02

TC1130

Advance Information

Functional Description

The basic structure and external interconnections of the DMA are shown in Figure

Clock Control
f DMA

DMA Controller

Address Decoder

Arbiter/ Switch Control
4 MultiCAN
2 ASC0
2 ASC1
2 ASC2

SSC0
2 SSC1
1 CCU60
1 CCU61
4 MLI0
4 MLI1

DMA Request Wiring

Matrix
1 I2C

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived SAF-TC1130-L100EBBB Datasheet file may be downloaded here without warranties.

Datasheet ID: SAF-TC1130-L100EBBB 638679