ADC0804S050TS/C1,1

ADC0804S050TS/C1,1 Datasheet

ADC0804S030/040/050

Part	Datasheet
ADC0804S050TS/C1,1	ADC0804S050TS/C1,1 (pdf)

Related Parts	Information
ADC0804S040TS/C1,1	ADC0804S040TS/C1,1
ADC0804S030TS/C1,1	ADC0804S030TS/C1,1

PDF Datasheet Preview
ADC0804S030/040/050 Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz The ADC0806030/040/050 are a family of 8-bit high-speed, low-power Analog-to-Digital Converters ADC for professional video and other applications. It converts the analog input signal into 8-bit binary coded digital signals at a maximum sampling rate of 50 MHz. All digital inputs and outputs are Transistor-Transistor Logic TTL and CMOS compatible, although a low-level sine wave clock input signal can also be used. The device requires an external source to drive its reference ladder. If the application requires that the reference is driven via internal sources, IDT recommends you use one of the ADC1003S030/040/050 family. 8-bit resolution Sampling rate up to 50 MHz DC sampling allowed One clock cycle conversion only High signal-to-noise ratio over a large analog input frequency range effective bits at MHz full-scale input at fclk = 40 MHz No missing codes guaranteed In-Range IR CMOS output TTL and CMOS levels compatible digital inputs 3 V to 5 V CMOS digital outputs Low-level AC clock input signal allowed External reference voltage regulator Power dissipation only 175 mW typical Low analog input capacitance, no buffer amplifier required No sample-and-hold circuit required Video data digitizing Radar Transient signal analysis modulators Medical imaging Barcode scanner Global Positioning System GPS receiver Integrated Device Technology ADC0804S030/040/050 Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz Cellular base stations Quick reference data Table Quick reference data VCCA = V3 to V4 = V to V VCCD = V11 to V12 and V28 to V27 = V to V VCCO = V13 to V14 = V to V AGND and DGND shorted together Tamb = 0 C to 70 C typical values measured at VCCA = VCCD = 5 V and VCCO = V, Vi a p-p = V CL = 15 pF and Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VCCA VCCD VCCO ICCA ICCD ICCO analog supply voltage digital supply voltage output supply voltage analog supply current digital supply current output supply current fclk = 40 MHz ramp input integral non-linearity fclk = 40 MHz ramp input differential non-linearity fclk = 40 MHz ramp input fclk max maximum clock frequency ADC0804S030TS ADC0804S040TS ADC0804S050TS Ptot total power dissipation fclk = 40 MHz; ramp input 175 247 mW Ordering information Table Ordering information Type number Package Name ADC0804S030TS SSOP28 ADC0804S040TS SSOP28 ADC0804S050TS SSOP28 plastic shrink small outline package 28 leads body width mm plastic shrink small outline package 28 leads body width mm plastic shrink small outline package 28 leads body width mm Version Sampling frequency MHz SOT341-1 30 SOT341-1 40 SOT341-1 50 ADC0804S030_040_050_3 IDT All rights reserved. 2 of 18 Integrated Device Technology Block diagram ADC0804S030/040/050 Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz VCCA 3 CLK 1 CLOCK DRIVER VCCD2 analog VI 8 voltage input Rlad ANALOG - TO - DIGITAL CONVERTER LATCHES CMOS OUTPUTS 25 D7 24 D6 23 D5 22 D4 21 D3 20 D2 19 D1 18 D0 MSB data outputs LSB RB 6 ADC0804S030 4 AGND analog ground Fig Block diagram 12 DGND2 digital ground VCCO IN-RANGE LATCH 26 CMOS OUTPUT 14 OGND 27 DGND1 Ordering information 2 Alternative parts 15 Block diagram 3 13 Package outline. 16 Pinning information 4 14 Pinning 4 15 Pin description 4 16 Limiting values. 5 Contact information 17 Contents. 18 ADC0804S030_040_050_3 IDT All rights reserved. 18 of 18

PDF Datasheet Preview

ADC0804S030/040/050

Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz

The ADC0806030/040/050 are a family of 8-bit high-speed, low-power Analog-to-Digital Converters ADC for professional video and other applications. It converts the analog input signal into 8-bit binary coded digital signals at a maximum sampling rate of 50 MHz. All digital inputs and outputs are Transistor-Transistor Logic TTL and CMOS compatible, although a low-level sine wave clock input signal can also be used.

The device requires an external source to drive its reference ladder. If the application requires that the reference is driven via internal sources, IDT recommends you use one of the ADC1003S030/040/050 family.
8-bit resolution Sampling rate up to 50 MHz DC sampling allowed One clock cycle conversion only High signal-to-noise ratio over a large analog input frequency range effective bits
at MHz full-scale input at fclk = 40 MHz No missing codes guaranteed In-Range IR CMOS output TTL and CMOS levels compatible digital inputs 3 V to 5 V CMOS digital outputs Low-level AC clock input signal allowed External reference voltage regulator Power dissipation only 175 mW typical Low analog input capacitance, no buffer amplifier required No sample-and-hold circuit required

Video data digitizing Radar Transient signal analysis modulators Medical imaging Barcode scanner Global Positioning System GPS receiver

Integrated Device Technology

ADC0804S030/040/050

Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz

Cellular base stations

Quick reference data

Table Quick reference data

VCCA = V3 to V4 = V to V VCCD = V11 to V12 and V28 to V27 = V to V VCCO = V13 to V14 = V to V AGND and DGND shorted together Tamb = 0 C to 70 C typical values measured at VCCA = VCCD = 5 V and VCCO = V, Vi a p-p = V CL = 15 pF and Tamb = 25 C unless otherwise specified.

Symbol Parameter

Conditions

Min Typ Max Unit

VCCA VCCD VCCO ICCA ICCD ICCO
analog supply voltage digital supply voltage output supply voltage analog supply current digital supply current output supply current
fclk = 40 MHz ramp input
integral non-linearity
fclk = 40 MHz
ramp input
differential non-linearity fclk = 40 MHz ramp input
fclk max
maximum clock frequency

ADC0804S030TS ADC0804S040TS

ADC0804S050TS

Ptot
total power dissipation fclk = 40 MHz;
ramp input
175 247 mW
Ordering information
Table Ordering information

Type number

Package

Name

ADC0804S030TS SSOP28 ADC0804S040TS SSOP28 ADC0804S050TS SSOP28
plastic shrink small outline package 28 leads body width mm
plastic shrink small outline package 28 leads body width mm
plastic shrink small outline package 28 leads body width mm

Version

Sampling frequency MHz

SOT341-1 30

SOT341-1 40

SOT341-1 50

ADC0804S030_040_050_3

IDT All rights reserved.
2 of 18

Integrated Device Technology

Block diagram

ADC0804S030/040/050

Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz

VCCA 3

CLK 1

CLOCK DRIVER

VCCD2
analog VI 8 voltage input

Rlad

ANALOG - TO - DIGITAL CONVERTER

LATCHES

CMOS OUTPUTS
25 D7 24 D6 23 D5 22 D4 21 D3 20 D2 19 D1 18 D0

MSB data outputs LSB

RB 6 ADC0804S030
4 AGND analog ground

Fig Block diagram
12 DGND2
digital ground

VCCO

IN-RANGE LATCH
26 CMOS OUTPUT
14 OGND
27 DGND1
Ordering information 2

Alternative parts 15

Block diagram 3 13

Package outline. 16

Pinning information 4 14

Pinning 4 15

Pin description 4 16

Limiting values. 5

Contact information 17 Contents. 18

ADC0804S030_040_050_3

IDT All rights reserved.
18 of 18

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Datasheet ID: ADC0804S050TS/C1,1 636923