NDS8852H

NDS8852H Datasheet

NDS8852H Complementary MOSFET Half Bridge

Part	Datasheet
NDS8852H	NDS8852H (pdf)

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February 1996 NDS8852H Complementary MOSFET Half Bridge These Complementary MOSFET half bridge devices are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage half bridge applications or CMOS applications when both gates are connected together. N-Channel 4.3A, 30V, VGS=10V. P-Channel -3.4A, -30V, VGS=-10V. High density cell design or extremely low RDS ON . High power and current handling capability in a widely used surface mount package. Matched pair for equal input capacitance and power capability P-Gate N -Gate Vout Absolute Maximum Ratings Symbol Parameter TA= 25°C unless otherwise noted N-Channel VDSS Drain-Source Voltage VGSS Gate-Source Voltage Drain Current - Continuous - Pulsed Note 1a & 2 Maximum Power Dissipation Single Device Note 1a Note 1b TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS Note 1c Thermal Resistance, Junction-to-Ambient Single Device Thermal Resistance, Junction-to-Case Single Device Note 1a Note 1 1 -55 to 150 P-Channel -30 -20 -10 Units V A °C/W °C/W 1997 Fairchild Semiconductor Corporation Electrical Characteristics TA = 25°C unless otherwise noted Symbol Parameter Conditions OFF CHARACTERISTICS BVDSS IDSS Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = 250 µA VGS = 0 V, ID = -250 µA VDS = 24 V, VGS = 0 V VDS = -24 V, VGS = 0 V IGSSF Gate - Body Leakage, Forward

PDF Datasheet Preview

February 1996

NDS8852H Complementary MOSFET Half Bridge

These Complementary MOSFET half bridge devices are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage half bridge applications or CMOS applications when both gates are connected together.

N-Channel 4.3A, 30V, VGS=10V. P-Channel -3.4A, -30V, VGS=-10V.

High density cell design or extremely low RDS ON . High power and current handling capability in a widely used surface mount package.

Matched pair for equal input capacitance and power capability

P-Gate N -Gate

Vout

Absolute Maximum Ratings

Symbol Parameter

TA= 25°C unless otherwise noted N-Channel

VDSS

Drain-Source Voltage

VGSS

Gate-Source Voltage

Drain Current - Continuous
- Pulsed

Note 1a & 2

Maximum Power Dissipation

Single Device

Note 1a Note 1b

TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS

Note 1c

Thermal Resistance, Junction-to-Ambient Single Device

Thermal Resistance, Junction-to-Case Single Device

Note 1a Note 1
1 -55 to 150

P-Channel -30 -20 -10

Units V A
°C/W °C/W
1997 Fairchild Semiconductor Corporation

Electrical Characteristics TA = 25°C unless otherwise noted

Symbol Parameter

Conditions

OFF CHARACTERISTICS

BVDSS IDSS

Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current

VGS = 0 V, ID = 250 µA VGS = 0 V, ID = -250 µA VDS = 24 V, VGS = 0 V

VDS = -24 V, VGS = 0 V

IGSSF

Gate - Body Leakage, Forward

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Datasheet ID: NDS8852H 634614