MM74C48N

MM74C48N Datasheet

MM74C48 BCD-to-7 Segment Decoder

Part	Datasheet
MM74C48N	MM74C48N (pdf)

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MM74C48 BCD-to-7 Segment Decoder MM74C48 BCD-to-7 Segment Decoder The MM74C48 BCD-to-7 segment decoder is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement transistors. Seven NAND gates and one driver are connected in pairs to make binary-coded decimal BCD data and its complement available to the seven decoding AND-OR-INVERT gates. The remaining NAND gate and three input buffers provide test-blanking input/ripple-blanking output, and ripple-blanking inputs. s Wide supply voltage range 3.0V to 15V s Guaranteed noise margin 1.0V s High noise immunity VCC typ. s Low power TTL compatibility: fan out of 2 driving 74L s High current sourcing output up to 50 mA s Ripple blanking for leading or trailing zeros optional s Lamp test provision Ordering Code: Order Number Package Number Package Description MM74C48N N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Connection Diagrams Segment Identification Numerical Designations and Resultant Displays Top View 2002 Fairchild Semiconductor Corporation DS005883 MM74C48 Truth Table Decimal Inputs Outputs BI/RBO Note Function LT RBI D C B A Note 1 a b c d e f g HHL L H L Note 2 HXL L LH L H L Note 2 HXL LHL HH L HH L H HX L LHH HHHH L LH HXLHL L LHH L LHH HX LH L H H L HH L HH HX LHHL HX LHHH HHH L HXHL L HXHL LH HHH L LHH HXHLHL L LHHLH HXH L HH L LHHL LH

PDF Datasheet Preview

MM74C48 BCD-to-7 Segment Decoder

MM74C48 BCD-to-7 Segment Decoder

The MM74C48 BCD-to-7 segment decoder is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement transistors. Seven NAND gates and one driver are connected in pairs to make binary-coded decimal BCD data and its complement available to the seven decoding AND-OR-INVERT gates. The remaining NAND gate and three input buffers provide test-blanking input/ripple-blanking output, and ripple-blanking inputs.
s Wide supply voltage range 3.0V to 15V s Guaranteed noise margin 1.0V s High noise immunity VCC typ. s Low power TTL compatibility:
fan out of 2 driving 74L s High current sourcing output up to 50 mA s Ripple blanking for leading or trailing zeros optional s Lamp test provision
Ordering Code:

Order Number Package Number

Package Description

MM74C48N

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

Connection Diagrams

Segment Identification

Numerical Designations and Resultant Displays

Top View
2002 Fairchild Semiconductor Corporation DS005883

MM74C48

Truth Table

Decimal

Inputs

Outputs

BI/RBO

Note

Function LT RBI D C B A Note 1 a b c d e f g

HHL L

H L Note 2

HXL L LH

L H L Note 2

HXL LHL

HH L HH L H

HX L LHH

HHHH L LH

HXLHL L

LHH L LHH

HX LH L H

H L HH L HH

HX LHHL

HX LHHH

HHH L

HXHL L

HXHL LH

HHH L LHH

HXHLHL

L LHHLH

HXH L HH

L LHHL LH

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Datasheet ID: MM74C48N 634353