N25Q064A13E5340F TR

N25Q064A13E5340F TR Datasheet

3V, Multiple I/O, 4KB Sector Erase N25Q064A

Part	Datasheet
N25Q064A13E5340F TR	N25Q064A13E5340F TR (pdf)

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64Mb, 3V, Multiple I/O Serial Flash Memory Features Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q064A • SPI-compatible serial bus interface • 108 MHz MAX clock frequency • single supply voltage • Dual/quad I/O instruction provides increased throughput up to 432 MHz • Supported protocols Extended SPI, dual I/O, and quad I/O • Execute-in-place XIP mode for all three protocols Configurable via volatile or nonvolatile registers Enables memory to work in XIP mode directly af- ter power-on • PROGRAM/ERASE SUSPEND operations • Continuous read of entire memory via a single com- mand Fast read Quad or dual output fast read Quad or dual I/O fast read • Flexible to fit application Configurable number of dummy cycles Output buffer configurable • 64-byte, user-lockable, one-time programmable OTP dedicated area • Erase capability Subsector erase 4KB uniform granularity blocks Sector erase 64KB uniform granularity blocks Full-chip erase • Write protection Software write protection applicable to every 64KB sector via volatile lock bit Hardware write protection protected area size defined by five nonvolatile bits BP0, BP1, BP2, BP3, and TB Additional smart protections, available upon request • Electronic signature JEDEC-standard 2-byte signature BA17h Unique ID code UID 17 read-only bytes, including: • Two additional extended device ID EDID bytes to identify device factory options • Customized factory data 14 bytes • Minimum 100,000 ERASE cycles per sector • More than 20 years data retention • Packages JEDEC standard, all RoHS compliant F6 = V-PDFN-8 6mm x 5mm MLP8 6mm x 5mm F8 = V-PDFN-8 8mm x 6mm MLP8 8mm x 6mm 12 = T-PBGA-24b05 6mm x 8mm 14 = T-PBGA-24b05 6mm x 8mm, 4x6 ball array SF = SOP2-16 300 mils body width SO16W SE = SOP2-8 208 mils body width SO8W 53 = XF-SCSP-8/2.93mm x 3.5mm XFCSP Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 64Mb, 3V, Multiple I/O Serial Flash Memory Features Contents Device Description 6 Features 6 Operating Protocols 6 XIP Mode 6 Device Configurability 7 Signal Assignments 8 Signal Descriptions 11 Memory Organization 13 Memory Configuration and Block Diagram 13 Memory Map 64Mb Density 14 Device Protection 15 Serial Peripheral Interface Modes 17 SPI Protocols 19 Nonvolatile and Volatile Registers 20 Status Register 21 Nonvolatile and Volatile Configuration Registers 22 Enhanced Volatile Configuration Register 24 Flag Status Register 25 Command Definitions 27 READ REGISTER and WRITE REGISTER Operations 29 READ STATUS REGISTER or FLAG STATUS REGISTER Command 29 READ NONVOLATILE CONFIGURATION REGISTER Command 29 READ VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command 30 WRITE STATUS REGISTER Command 30 WRITE NONVOLATILE CONFIGURATION REGISTER Command 31 WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command 31 READ LOCK REGISTER Command 32 WRITE LOCK REGISTER Command 33 CLEAR FLAG STATUS REGISTER Command 34 READ IDENTIFICATION Operations 35 READ ID and MULTIPLE I/O READ ID Commands 35 READ SERIAL FLASH DISCOVERY PARAMETER Command 36 READ MEMORY Operations 39 PROGRAM Operations 43 WRITE Operations 48 WRITE ENABLE Command 48 WRITE DISABLE Command 48 ERASE Operations 50 SUBSECTOR ERASE Command 50 SECTOR ERASE Command 50 BULK ERASE Command 51 PROGRAM/ERASE SUSPEND Command 52 PROGRAM/ERASE RESUME Command 54 ONE TIME PROGRAMMABLE Operations 55 READ OTP ARRAY Command 55 PROGRAM OTP ARRAY Command 55 XIP Mode 58 Activate or Terminate XIP Using Volatile Configuration Register 58 Activate or Terminate XIP Using Nonvolatile Configuration Register 58 Confirmation Bit Settings Required to Activate or Terminate XIP 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 64Mb, 3V, Multiple I/O Serial Flash Memory Features Terminating XIP After a Controller and Memory Reset 60 Power-Up and Power-Down 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 64Mb, 3V, Multiple I/O Serial Flash Memory Features List of Figures Figure 1 Logic Diagram 7 Figure 2 8-Pin, VDFPN8 MLP8 and SOP2 SO8W Top View 8 Figure 3 16-Pin, Plastic Small Outline SO16 Top View 8 Figure 4 24-Ball TBGA , 5 x 5 Balls Down 9 Figure 5 24-Ball TBGA, 4 x 6 Balls Down 9 Figure 6 12-Ball XF-SCSP, 4 x 6 Balls Down 10 Figure 7 Block Diagram 13 Figure 8 Bus Master and Memory Devices on the SPI Bus 18 Figure 9 SPI Modes 18 Figure 10 Internal Configuration Register 20 Figure 11 READ REGISTER Command 29 Figure 12 WRITE REGISTER Command 31 Figure 13 READ LOCK REGISTER Command 33 Figure 14 WRITE LOCK REGISTER Command 34 Figure 15 READ ID and MULTIPLE I/O Read ID Commands 36 Figure 16 READ Command 40 Figure 17 FAST READ Command 40 Figure 18 DUAL OUTPUT FAST READ 41 Figure 19 DUAL INPUT/OUTPUT FAST READ Command 41 Figure 20 QUAD OUTPUT FAST READ Command 42 Figure 21 QUAD INPUT/OUTPUT FAST READ Command 42 Figure 22 PAGE PROGRAM Command 44 Figure 23 DUAL INPUT FAST PROGRAM Command 45 Figure 24 EXTENDED DUAL INPUT FAST PROGRAM Command 45 Figure 25 QUAD INPUT FAST PROGRAM Command 46 Figure 26 EXTENDED QUAD INPUT FAST PROGRAM Command 47 Figure 27 WRITE ENABLE and WRITE DISABLE Command Sequence 49 Figure 28 SUBSECTOR and SECTOR ERASE Command 51 Figure 29 BULK ERASE Command 52 Figure 30 READ OTP Command 55 Figure 31 PROGRAM OTP Command 57 Figure 32 XIP Mode Directly After Power-On 59 Figure 33 Power-Up Timing 61 Figure 34 Reset AC Timing During PROGRAM or ERASE Cycle 64 Figure 35 Serial Input Timing 64 Figure 36 Write Protect Setup and Hold During WRITE STATUS REGISTER Operation SRWD = 1 65 Figure 37 Hold Timing 65 Figure 38 Output Timing 66 Figure 39 VPPH Timing 66 Figure 40 AC Timing Input/Output Reference Levels 69 Figure 41 V-PDFN-8 6mm x 5mm MLP8 Package Code F6 73 Figure 42 V-PDFN-8 8mm x 6mm MLP8 Package Code F8 74 Figure 43 T-PBGA-24b05 6mm x 8mm Package Code 12 75 Figure 44 T-PBGA-24b05 6mm x 8mm Package Code 14 76 Figure 45 SOP2-16 300 mils body width Package Code SF 77 Figure 46 SOP2-8 208 mils body width Package Code SE 78 Figure 47 XF-SCSP-8/2.93mm x 3.5mm Package Code 53 79 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 64Mb, 3V, Multiple I/O Serial Flash Memory Features List of Tables Table 1 Signal Descriptions 11 Table 2 Sectors[127:0] 14 Table 3 Data Protection using Device Protocols 15 Table 4 Memory Sector Protection Truth Table 15 Table 5 Protected Area Sizes Upper Area 15 Table 6 Protected Area Sizes Lower Area 16 Table 7 SPI Modes 17 Table 8 Extended, Dual, and Quad SPI Protocols 19 Table 9 Status Register Bit Definitions 21 Table 10 Nonvolatile Configuration Register Bit Definitions 22 Table 11 Volatile Configuration Register Bit Definitions 23 Table 12 Sequence of Bytes During Wrap 24 Table 13 Supported Clock Frequencies 24 Table 14 Enhanced Volatile Configuration Register Bit Definitions 24 Table 15 Flag Status Register Bit Definitions 25 Table 16 Command Set 27 Table 17 Lock Register 32 Table 18 Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands 35 Table 19 Read ID Data Out 35 Table 20 Extended Device ID, First Byte 35 Table 21 Serial Flash Discovery Parameter Header Structure 37 Table 22 Parameter ID 37 Table 23 Command/Address/Data Lines for READ MEMORY Commands 39 Table 24 Data/Address Lines for PROGRAM Commands 43 Table 25 Operations Allowed/Disallowed During Device States 53 Table 26 OTP Control Byte 64 56 Table 27 XIP Confirmation Bit 59 Table 28 Effects of Running XIP in Different Protocols 59 Table 29 Power-Up Timing and VWI Threshold 62 Table 30 AC RESET Conditions 63 Table 31 Suspend Parameters 67 Table 32 Absolute Ratings 68 Table 33 Operating Conditions 68 Table 34 Input/Output Capacitance 68 Table 35 AC Timing Input/Output Conditions 69 Table 36 DC Current Characteristics and Operating Conditions 70 Table 37 DC Voltage Characteristics and Operating Conditions 70 Table 38 AC Characteristics and Operating Conditions 71 Table 39 Part Number Information 80 Table 40 Package Details 81 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 64Mb, 3V, Multiple I/O Serial Flash Memory Device Description Device Description The N25Q is the first high-performance multiple input/output serial Flash memory device manufactured on 65nm NOR technology. It features execute-in-place XIP functionality, advanced write protection mechanisms, and a high-speed SPI-compatible bus interface. The innovative, high-performance, dual and quad input/output instructions enable double or quadruple the transfer bandwidth for READ and PROGRAM operations. The memory is organized as 128 64KB main sectors that are further divided into 16 subsectors each 2048 subsectors in total . The memory can be erased one 4KB subsector at a time, 64KB sectors at a time, or as a whole. The memory can be write protected by software through volatile and nonvolatile protection features, depending on the application needs. The protection granularity is of 64KB sector granularity for volatile protections The device has 64 one-time programmable OTP bytes that can be read and programmed with the READ OTP and PROGRAM OTP commands. These 64 bytes can also be permanently locked with a PROGRAM OTP command. The device also has the ability to pause and resume PROGRAM and ERASE cycles by using dedicated PROGRAM/ERASE SUSPEND and RESUME instructions. Operating Protocols The memory can be operated with three different protocols: • Extended SPI standard SPI protocol upgraded with dual and quad operations • Dual I/O SPI • Quad I/O SPI The standard SPI protocol is extended and enhanced by dual and quad operations. In addition, the dual SPI and quad SPI protocols improve the data access time and throughput of a single I/O device by transmitting commands, addresses, and data across two or four data lines. XIP Mode XIP mode requires only an address no instruction to output data, improving random access time and eliminating the need to shadow code onto RAM for fast execution. All protocols support XIP operation. For flexibility, multiple XIP entry and exit methods are available. For applications that must enter XIP mode immediately after powering up, XIP mode can be set as the default mode through the nonvolatile configuration register bits. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 64Mb, 3V, Multiple I/O Serial Flash Memory Device Description Device Configurability The N25Q family offers additional features that are configured through the nonvolatile configuration register for default and/or nonvolatile settings. Volatile settings can be configured through the volatile and volatile-enhanced configuration registers. These configurable features include the following • Number of dummy cycles for the fast READ commands • Output buffer impedance • SPI protocol types extended SPI, DIO-SPI, or QIO-SPI • Required XIP mode • Enabling/disabling HOLD RESET function • Enabling/disabling wrap mode Figure 1 Logic Diagram DQ0 C S# VPP/W#/DQ2 HOLD#/DQ3 VSS Note Reset functionality is available in devices with a dedicated part number. See Part Num- ber Ordering Information for more details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. Signal Assignments 64Mb, 3V, Multiple I/O Serial Flash Memory Signal Assignments Figure 2 8-Pin, VDFPN8 MLP8 and SOP2 SO8W Top View DQ1 2 W#/VPP/DQ2 3 VSS 4 8 VCC 7 HOLD#/DQ3 5 DQ0 On the underside of the MLP8 package, there is an exposed central pad that is pulled internally to VSS and must not be connected to any other voltage or signal line on the PCB. Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for complete package names and details. Figure 3 16-Pin, Plastic Small Outline SO16 Top View HOLD#/DQ3 1 VCC 2 DNU 3 DNU 4 DNU 5 DNU 6 S# 7 DQ1 8 16 C 15 DQ0 14 DNU 13 DNU 12 DNU 11 DNU 10 VSS 9 W#/VPP/DQ2 Note Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for complete package names and details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 64Mb, 3V, Multiple I/O Serial Flash Memory Signal Assignments Figure 4 24-Ball TBGA , 5 x 5 Balls Down NC W#/VPP/DQ2 NC DQ1 DQ0 HOLD#/DQ3 NC Note See Part Number Ordering Information for complete package names and details. Figure 5 24-Ball TBGA, 4 x 6 Balls Down NC W#/VPP/DQ2 DQ1 DQ0 HOLD#/DQ3 Note See Part Number Ordering Information for complete package names and details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 64Mb, 3V, Multiple I/O Serial Flash Memory Signal Assignments Figure 6 12-Ball XF-SCSP, 4 x 6 Balls Down HOLD#/DQ3 W#/ VPP /DQ2 Note See Part Number Ordering Information for complete package names and details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 64Mb, 3V, Multiple I/O Serial Flash Memory Signal Descriptions Signal Descriptions The signal description table below is a comprehensive list of signals for the N25 family devices. All signals listed may not be supported on this device. See Signal Assignments for information specific to this device. Table 1 Signal Descriptions Symbol C S# DQ2 DQ3 RESET# Type Input Input and I/O Output and I/O Input and I/O Input and I/O Control Input Clock Provides the timing of the serial interface. Commands, addresses, or data present at serial data inputs are latched on the rising edge of the clock. Data is shifted out on the falling edge of the clock. Chip select When S# is HIGH, the device is deselected and DQ1 is at High-Z. When in extended SPI mode, with the device deselected, DQ1 is tri-stated. Unless an internal PROGRAM, ERASE, or WRITE STATUS REGISTER cycle is in progress, the device enters standby power mode not deep power-down mode . Driving S# LOW enables the device, placing it in the active power mode. After power-up, a falling edge on S# is required prior to the start of any command. Serial data Transfers data serially into the device. It receives command codes, addresses, and the data to be programmed. Values are latched on the rising edge of the clock. DQ0 is used for input/output during the following operations DUAL OUTPUT FAST READ, QUAD OUTPUT FAST READ, DUAL INPUT/OUTPUT FAST READ, and QUAD INPUT/OUTPUT FAST READ. When used for output, data is shifted out on the falling edge of the clock. In DIO-SPI, DQ0 always acts as an input/output. In QIO-SPI, DQ0 always acts as an input/output, with the exception of the PROGRAM or ERASE cycle performed with VPP. The device temporarily enters the extended SPI protocol and then returns to QIO-SPI as soon as VPP goes LOW. Serial data:Transfers data serially out of the device. Data is shifted out on the falling edge of the clock. DQ1 is used for input/output during the following operations DUAL INPUT FAST PROGRAM, QUAD INPUT FAST PROGRAM, DUAL INPUT EXTENDED FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. When used for input, data is latched on the rising edge of the clock. In DIO-SPI, DQ1 always acts as an input/output. In QIO-SPI, DQ1 always acts as an input/output, with the exception of the PROGRAM or ERASE cycle performed with the enhanced program supply voltage VPP . In this case the device temporarily enters the extended SPI protocol and then returns to QIO-SPI as soon as VPP goes LOW. DQ2 When in QIO-SPI mode or in extended SPI mode using QUAD FAST READ commands, the signal functions as DQ2, providing input/output. All data input drivers are always enabled except when used as an output. Micron recommends customers drive the data signals normally to avoid unnecessary switching current and float the signals before the memory device drives data on them. DQ3 When in quad SPI mode or in extended SPI mode using quad FAST READ commands, the signal functions as DQ3, providing input/output. HOLD# is disabled and RESET# is disabled if the device is selected. RESET This is a hardware RESET# signal. When RESET# is driven HIGH, the memory is in the normal operating mode. When RESET# is driven LOW, the memory enters reset mode and output is High-Z. If RESET# is driven LOW while an internal WRITE, PROGRAM, or ERASE operation is in progress, data may be lost. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 64Mb, 3V, Multiple I/O Serial Flash Memory Signal Descriptions Table 1 Signal Descriptions Continued Symbol HOLD# VCC VSS DNU NC Type Control Input Control Input Power Power Ground HOLD Pauses any serial communications with the device without deselecting the device. DQ1 output is High-Z. DQ0 input and the clock are "Don't Care." To enable HOLD, the device must be selected with S# driven LOW. HOLD# is used for input/output during the following operations QUAD OUTPUT FAST READ, QUAD INPUT/OUTPUT FAST READ, QUAD INPUT FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. In QIO-SPI, HOLD# acts as an I/O DQ3 functionality , and the HOLD# functionality is disabled when the device is selected. When the device is deselected S# is HIGH in parts with RESET# functionality, it is possible to reset the device unless this functionality is not disabled by means of dedicated registers bits. The HOLD# functionality can be disabled using bit 4 of the NVCR or bit 4 of the VECR. Write protect W# can be used as a protection control input or in QIO-SPI operations. When in extended SPI with single or dual commands, the WRITE PROTECT function is selectable by the voltage range applied to the signal. If voltage range is low 0V to VCC , the signal acts as a write protection control input. The memory size protected against PROGRAM or ERASE operations is locked as specified in the status register block protect bits W# is used as an input/output DQ2 functionality during QUAD INPUT FAST READ and QUAD INPUT/OUTPUT FAST READ operations and in QIO-SPI. Supply voltage If VPP is in the voltage range of VPPH, the signal acts as an additional power supply, as defined in the AC Measurement Conditions table. During QIFP, QIEFP, and QIO-SPI PROGRAM/ERASE operations, it is possible to use the additional VPP power supply to speed up internal operations. However, to enable this functionality, it is necessary to set bit 3 of the VECR to In this case, VPP is used as an I/O until the end of the operation. After the last input data is shifted in, the application should apply VPP voltage to VPP within 200ms to speed up the internal operations. If the VPP voltage is not applied within 200ms, the PROGRAM/ERASE operations start at standard speed. The default value of VECR bit 3 is 1, and the VPP functionality for quad I/O modify operations is disabled. Device core power supply Source voltage. Ground Reference for the VCC supply voltage. Do not use. No connect. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 64Mb, 3V, Multiple I/O Serial Flash Memory Organization Memory Organization Memory Configuration and Block Diagram Each page of memory can be individually programmed. Bits are programmed from one through zero. The device is subsector, sector, or bulk-erasable, but not page-erasable. Bits are erased from zero through one. The memory is configured as 8,388,608 bytes 8 bits each 128 sectors 64KB each 2048 subsectors 4KB each and 37,768 pages 256 bytes each and 64 OTP bytes are located outside the main memory array. Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 64Mb, 3V, Multiple I/O Serial Flash Memory Package Dimensions aaa C NE - 1 x TYP eee M C A B fff M C Figure 42 V-PDFN-8 8mm x 6mm MLP8 Package Code F8 A B TYP TYP/ 1 MAX TYP Pin 1 ID aaa C Pin 1 ID R TYP 6 2 TYP bbb C ddd C Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 64Mb, 3V, Multiple I/O Serial Flash Memory Package Dimensions Figure 43 T-PBGA-24b05 6mm x 8mm Package Code 12 Seating plane A 54321 Ball A1 ID A B C 8 D E Ball A1 ID Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 64Mb, 3V, Multiple I/O Serial Flash Memory Package Dimensions Figure 44 T-PBGA-24b05 6mm x 8mm Package Code 14 Seating plane 24X Dimensions apply to solder balls postreflow on SMD ball pads. 5 CTR 8 1 TYP Ball A1 ID 432 1 A B C D E F Ball A1 ID 1 TYP 3 CTR 6 Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 64Mb, 3V, Multiple I/O Serial Flash Memory Package Dimensions Figure 45 SOP2-16 300 mils body width Package Code SF MIN/ MAX h x 45° MIN/ MAX 0° MIN/8° MAX MIN/ MAX TYP Z MIN/ MAX Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 64Mb, 3V, Multiple I/O Serial Flash Memory Package Dimensions Figure 46 SOP2-8 208 mils body width Package Code SE MIN/ MAX MIN/ MAX MIN/ MAX MIN/ MAX MIN/ MAX MIN/ MAX MIN/ MAX MIN/ MAX 0º MIN/ 10º MAX MIN/ MAX Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 64Mb, 3V, Multiple I/O Serial Flash Memory Package Dimensions Figure 47 XF-SCSP-8/2.93mm x 3.5mm Package Code 53 12X Dimensions apply to solder balls postreflow on UBM ball pads. 4321 A B C D E F Seating plane A Ball A1 ID Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 64Mb, 3V, Multiple I/O Serial Flash Memory Part Number Ordering Information Part Number Ordering Information Micron Serial NOR Flash devices are available in different configurations and densities. Verify valid part numbers by using Micron’s part catalog search at micron.com. To compare features and specifications by device type, visit micron.com/products. Contact the factory for devices not found. For more information on how to identify products and top-side marking by the process identification letter, refer to technical note TN-12-24, "Serial Flash Memory Device Marking for the M25P, M25PE, M25PX, and N25Q Product Families." Table 39 Part Number Information Part Number Category Device type Density Technology Feature set Operating voltage Block structure Package RoHS-compliant Temperature and test flow Security features Shipping material Category Details N25Q = Serial NOR Flash memory, Multiple Input/Output Single, Dual, Quad I/O , XIP 064 = 64Mb A = 65nm 1 = Byte addressability HOLD pin Micron XIP 2 = Byte addressability HOLD pin Basic XIP 3 = Byte addressability RST# pin Micron XIP 4 = Byte addressability RST# pin Basic XIP 3 = VCC = to 3.6V E = Uniform 64KB and 4KB F6 = V-PDFN-8 6mm x 5mm MLP8 6mm x 5mm F8 = V-PDFN-8 8mm x 6mm MLP8 8mm x 6mm 12 = T-PBGA-24b05 6mm x 8mm 14 = T-PBGA-24b05 6mm x 8mm, 4x6 ball array SF = SOP2-16 300 mils body width SO16W SE = SOP2-8 208 mils body width SO8W 53 = XF-SCSP-8/2.93mm x 3.5mm XFCSP 4 = IT to +85°C Device tested with standard test flow A = Automotive temperature range to +125°C Device tested with high reliability certified test flow H = IT to +85°C Device tested with high reliability certified test flow 0 = Default E = Tray F = Tape and reel G = Tube Note Additional secure options are available upon customer request. Notes 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 64Mb, 3V, Multiple I/O Serial Flash Memory Part Number Ordering Information Table 40 Package Details Micron SPI and JEDEC Package Name V-PDFN-8 6mm x 5mm V-PDFN-8 8mm x 6mm T-PBGA24b05/6mm x T-PBGA24b05/6mm x 8mm 4x6 ball array SOP2- 16/ 300 mil SOP2- 8/ 208 mil XF-SCSP-8/ 2.93mm x 3.5mm Shortened Package Name DFN/6mm x 5mm DFN/8mm x 6mm TBGA 24 Package Description Very thin, plastic small-outline, 8 terminal pads no leads , 6mm x 5mm Very thin, plastic small outline, 8 terminal pads no leads , 8mm x 6mm Thin plastic ball grid array, 24 balls, 6mm x 8mm TBGA 24 Thin plastic ball grid array, 24 balls, 6mm x 8mm, 4x6 ball array SO16W SO8W XFCSP Small-outline integrated circuit, 16 pins, wide 300 mil Small-outline integrated circuit, 8-pins, wide 208 mil Wafer level, chip-scale package, 12 balls 8 active balls , 2.93mm x 3.5mm x 0.41mm M25P M45PE Symbol MF MW N25Q Symbol M25P M45PE Package Names MLP8, DFN8, VDFPN8, VFQFPN8 MLP8, VDFPN8 Alternate Package Name V-PSON1-8/6mm x 5mm, VSON V-PSON1-8/8mm x 6mm, VSON TBGA24 6mm x TBGA24 6mm x 4x6 ball array SO16 wide 300 SOIC-16/300 mil, mil body width SOP 16L 300 mil • Updated HOLD# description in Signal Description table • Updated SOP2-8 208 mils body width - Package Code SE in Package Dimensions • Updated the READ ID Operation figure in READ ID Operations • Updated ERASE Operations • Added link to part number chart in Part Number Ordering Information • Updated part numbers in Features • Updated tBE from 250 to 120 in AC Characteristics and Operating Conditions. • Updated part numbers • Updated tSSE specification in AC Reset Conditions table • Micron rebrand Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. • In Ordering Information, changed the following E = Uniform 4KB subsector erase and Uniform 64KB sector erase • Updated package information • Initial release 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel 208-368-4000 Sales inquiries 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.

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64Mb, 3V, Multiple I/O Serial Flash Memory Features

Micron Serial NOR Flash Memory
3V, Multiple I/O, 4KB Sector Erase N25Q064A
• SPI-compatible serial bus interface
• 108 MHz MAX clock frequency
• single supply voltage
• Dual/quad I/O instruction provides increased
throughput up to 432 MHz
• Supported protocols

Extended SPI, dual I/O, and quad I/O
• Execute-in-place XIP mode for all three protocols

Configurable via volatile or nonvolatile registers Enables memory to work in XIP mode directly af-
ter power-on
• PROGRAM/ERASE SUSPEND operations
• Continuous read of entire memory via a single com-
mand Fast read Quad or dual output fast read Quad or dual I/O fast read
• Flexible to fit application Configurable number of dummy cycles Output buffer configurable
• 64-byte, user-lockable, one-time programmable OTP dedicated area
• Erase capability Subsector erase 4KB uniform granularity blocks Sector erase 64KB uniform granularity blocks Full-chip erase
• Write protection Software write protection applicable to every 64KB sector via volatile lock bit Hardware write protection protected area size defined by five nonvolatile bits BP0, BP1, BP2, BP3, and TB Additional smart protections, available upon request
• Electronic signature JEDEC-standard 2-byte signature BA17h Unique ID code UID 17 read-only bytes, including:
• Two additional extended device ID EDID bytes to identify device factory options
• Customized factory data 14 bytes
• Minimum 100,000 ERASE cycles per sector
• More than 20 years data retention
• Packages JEDEC standard, all RoHS compliant

F6 = V-PDFN-8 6mm x 5mm MLP8 6mm x 5mm F8 = V-PDFN-8 8mm x 6mm MLP8 8mm x 6mm 12 = T-PBGA-24b05 6mm x 8mm 14 = T-PBGA-24b05 6mm x 8mm, 4x6 ball array SF = SOP2-16 300 mils body width SO16W SE = SOP2-8 208 mils body width SO8W 53 = XF-SCSP-8/2.93mm x 3.5mm XFCSP

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
64Mb, 3V, Multiple I/O Serial Flash Memory Features

Contents

Device Description 6 Features 6 Operating Protocols 6 XIP Mode 6 Device Configurability 7

Signal Assignments 8 Signal Descriptions 11 Memory Organization 13

Memory Configuration and Block Diagram 13 Memory Map 64Mb Density 14 Device Protection 15 Serial Peripheral Interface Modes 17 SPI Protocols 19 Nonvolatile and Volatile Registers 20

Status Register 21 Nonvolatile and Volatile Configuration Registers 22 Enhanced Volatile Configuration Register 24 Flag Status Register 25 Command Definitions 27 READ REGISTER and WRITE REGISTER Operations 29 READ STATUS REGISTER or FLAG STATUS REGISTER Command 29 READ NONVOLATILE CONFIGURATION REGISTER Command 29 READ VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command 30 WRITE STATUS REGISTER Command 30 WRITE NONVOLATILE CONFIGURATION REGISTER Command 31 WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command 31 READ LOCK REGISTER Command 32 WRITE LOCK REGISTER Command 33 CLEAR FLAG STATUS REGISTER Command 34 READ IDENTIFICATION Operations 35 READ ID and MULTIPLE I/O READ ID Commands 35 READ SERIAL FLASH DISCOVERY PARAMETER Command 36 READ MEMORY Operations 39 PROGRAM Operations 43 WRITE Operations 48 WRITE ENABLE Command 48 WRITE DISABLE Command 48 ERASE Operations 50 SUBSECTOR ERASE Command 50 SECTOR ERASE Command 50 BULK ERASE Command 51 PROGRAM/ERASE SUSPEND Command 52 PROGRAM/ERASE RESUME Command 54 ONE TIME PROGRAMMABLE Operations 55 READ OTP ARRAY Command 55 PROGRAM OTP ARRAY Command 55 XIP Mode 58 Activate or Terminate XIP Using Volatile Configuration Register 58 Activate or Terminate XIP Using Nonvolatile Configuration Register 58 Confirmation Bit Settings Required to Activate or Terminate XIP 59

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.
64Mb, 3V, Multiple I/O Serial Flash Memory Features

Terminating XIP After a Controller and Memory Reset 60 Power-Up and Power-Down 61
Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.
64Mb, 3V, Multiple I/O Serial Flash Memory Features

List of Figures

Figure 1 Logic Diagram 7 Figure 2 8-Pin, VDFPN8 MLP8 and SOP2 SO8W Top View 8 Figure 3 16-Pin, Plastic Small Outline SO16 Top View 8 Figure 4 24-Ball TBGA , 5 x 5 Balls Down 9 Figure 5 24-Ball TBGA, 4 x 6 Balls Down 9 Figure 6 12-Ball XF-SCSP, 4 x 6 Balls Down 10 Figure 7 Block Diagram 13 Figure 8 Bus Master and Memory Devices on the SPI Bus 18 Figure 9 SPI Modes 18 Figure 10 Internal Configuration Register 20 Figure 11 READ REGISTER Command 29 Figure 12 WRITE REGISTER Command 31 Figure 13 READ LOCK REGISTER Command 33 Figure 14 WRITE LOCK REGISTER Command 34 Figure 15 READ ID and MULTIPLE I/O Read ID Commands 36 Figure 16 READ Command 40 Figure 17 FAST READ Command 40 Figure 18 DUAL OUTPUT FAST READ 41 Figure 19 DUAL INPUT/OUTPUT FAST READ Command 41 Figure 20 QUAD OUTPUT FAST READ Command 42 Figure 21 QUAD INPUT/OUTPUT FAST READ Command 42 Figure 22 PAGE PROGRAM Command 44 Figure 23 DUAL INPUT FAST PROGRAM Command 45 Figure 24 EXTENDED DUAL INPUT FAST PROGRAM Command 45 Figure 25 QUAD INPUT FAST PROGRAM Command 46 Figure 26 EXTENDED QUAD INPUT FAST PROGRAM Command 47 Figure 27 WRITE ENABLE and WRITE DISABLE Command Sequence 49 Figure 28 SUBSECTOR and SECTOR ERASE Command 51 Figure 29 BULK ERASE Command 52 Figure 30 READ OTP Command 55 Figure 31 PROGRAM OTP Command 57 Figure 32 XIP Mode Directly After Power-On 59 Figure 33 Power-Up Timing 61 Figure 34 Reset AC Timing During PROGRAM or ERASE Cycle 64 Figure 35 Serial Input Timing 64 Figure 36 Write Protect Setup and Hold During WRITE STATUS REGISTER Operation SRWD = 1 65 Figure 37 Hold Timing 65 Figure 38 Output Timing 66 Figure 39 VPPH Timing 66 Figure 40 AC Timing Input/Output Reference Levels 69 Figure 41 V-PDFN-8 6mm x 5mm MLP8 Package Code F6 73 Figure 42 V-PDFN-8 8mm x 6mm MLP8 Package Code F8 74 Figure 43 T-PBGA-24b05 6mm x 8mm Package Code 12 75 Figure 44 T-PBGA-24b05 6mm x 8mm Package Code 14 76 Figure 45 SOP2-16 300 mils body width Package Code SF 77 Figure 46 SOP2-8 208 mils body width Package Code SE 78 Figure 47 XF-SCSP-8/2.93mm x 3.5mm Package Code 53 79

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64Mb, 3V, Multiple I/O Serial Flash Memory Features

List of Tables

Table 1 Signal Descriptions 11 Table 2 Sectors[127:0] 14 Table 3 Data Protection using Device Protocols 15 Table 4 Memory Sector Protection Truth Table 15 Table 5 Protected Area Sizes Upper Area 15 Table 6 Protected Area Sizes Lower Area 16 Table 7 SPI Modes 17 Table 8 Extended, Dual, and Quad SPI Protocols 19 Table 9 Status Register Bit Definitions 21 Table 10 Nonvolatile Configuration Register Bit Definitions 22 Table 11 Volatile Configuration Register Bit Definitions 23 Table 12 Sequence of Bytes During Wrap 24 Table 13 Supported Clock Frequencies 24 Table 14 Enhanced Volatile Configuration Register Bit Definitions 24 Table 15 Flag Status Register Bit Definitions 25 Table 16 Command Set 27 Table 17 Lock Register 32 Table 18 Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands 35 Table 19 Read ID Data Out 35 Table 20 Extended Device ID, First Byte 35 Table 21 Serial Flash Discovery Parameter Header Structure 37 Table 22 Parameter ID 37 Table 23 Command/Address/Data Lines for READ MEMORY Commands 39 Table 24 Data/Address Lines for PROGRAM Commands 43 Table 25 Operations Allowed/Disallowed During Device States 53 Table 26 OTP Control Byte 64 56 Table 27 XIP Confirmation Bit 59 Table 28 Effects of Running XIP in Different Protocols 59 Table 29 Power-Up Timing and VWI Threshold 62 Table 30 AC RESET Conditions 63 Table 31 Suspend Parameters 67 Table 32 Absolute Ratings 68 Table 33 Operating Conditions 68 Table 34 Input/Output Capacitance 68 Table 35 AC Timing Input/Output Conditions 69 Table 36 DC Current Characteristics and Operating Conditions 70 Table 37 DC Voltage Characteristics and Operating Conditions 70 Table 38 AC Characteristics and Operating Conditions 71 Table 39 Part Number Information 80 Table 40 Package Details 81

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64Mb, 3V, Multiple I/O Serial Flash Memory Device Description

Device Description

The N25Q is the first high-performance multiple input/output serial Flash memory device manufactured on 65nm NOR technology. It features execute-in-place XIP functionality, advanced write protection mechanisms, and a high-speed SPI-compatible bus interface. The innovative, high-performance, dual and quad input/output instructions enable double or quadruple the transfer bandwidth for READ and PROGRAM operations.

The memory is organized as 128 64KB main sectors that are further divided into 16 subsectors each 2048 subsectors in total . The memory can be erased one 4KB subsector at a time, 64KB sectors at a time, or as a whole.

The memory can be write protected by software through volatile and nonvolatile protection features, depending on the application needs. The protection granularity is of 64KB sector granularity for volatile protections

The device has 64 one-time programmable OTP bytes that can be read and programmed with the READ OTP and PROGRAM OTP commands. These 64 bytes can also be permanently locked with a PROGRAM OTP command.

The device also has the ability to pause and resume PROGRAM and ERASE cycles by using dedicated PROGRAM/ERASE SUSPEND and RESUME instructions.

Operating Protocols

The memory can be operated with three different protocols:
• Extended SPI standard SPI protocol upgraded with dual and quad operations
• Dual I/O SPI
• Quad I/O SPI

The standard SPI protocol is extended and enhanced by dual and quad operations. In addition, the dual SPI and quad SPI protocols improve the data access time and throughput of a single I/O device by transmitting commands, addresses, and data across two or four data lines.

XIP Mode

XIP mode requires only an address no instruction to output data, improving random access time and eliminating the need to shadow code onto RAM for fast execution.

All protocols support XIP operation. For flexibility, multiple XIP entry and exit methods are available. For applications that must enter XIP mode immediately after powering up, XIP mode can be set as the default mode through the nonvolatile configuration register bits.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.
64Mb, 3V, Multiple I/O Serial Flash Memory Device Description

Device Configurability

The N25Q family offers additional features that are configured through the nonvolatile configuration register for default and/or nonvolatile settings. Volatile settings can be configured through the volatile and volatile-enhanced configuration registers. These configurable features include the following
• Number of dummy cycles for the fast READ commands
• Output buffer impedance
• SPI protocol types extended SPI, DIO-SPI, or QIO-SPI
• Required XIP mode
• Enabling/disabling HOLD RESET function
• Enabling/disabling wrap mode

Figure 1 Logic Diagram

DQ0 C S#

VPP/W#/DQ2 HOLD#/DQ3

VSS Note Reset functionality is available in devices with a dedicated part number. See Part Num-
ber Ordering Information for more details.

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Signal Assignments
64Mb, 3V, Multiple I/O Serial Flash Memory Signal Assignments

Figure 2 8-Pin, VDFPN8 MLP8 and SOP2 SO8W Top View

DQ1 2

W#/VPP/DQ2 3 VSS 4
8 VCC 7 HOLD#/DQ3
5 DQ0

On the underside of the MLP8 package, there is an exposed central pad that is pulled internally to VSS and must not be connected to any other voltage or signal line on the PCB.
Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for complete package names and details.

Figure 3 16-Pin, Plastic Small Outline SO16 Top View

HOLD#/DQ3 1 VCC 2

DNU 3 DNU 4 DNU 5 DNU 6

S# 7 DQ1 8
16 C 15 DQ0 14 DNU 13 DNU 12 DNU 11 DNU 10 VSS
9 W#/VPP/DQ2
Note Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for complete package names and details.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.
64Mb, 3V, Multiple I/O Serial Flash Memory Signal Assignments

Figure 4 24-Ball TBGA , 5 x 5 Balls Down

NC W#/VPP/DQ2 NC

DQ1 DQ0 HOLD#/DQ3 NC
Note See Part Number Ordering Information for complete package names and details. Figure 5 24-Ball TBGA, 4 x 6 Balls Down

NC W#/VPP/DQ2

DQ1 DQ0 HOLD#/DQ3
Note See Part Number Ordering Information for complete package names and details.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.
64Mb, 3V, Multiple I/O Serial Flash Memory Signal Assignments

Figure 6 12-Ball XF-SCSP, 4 x 6 Balls Down

HOLD#/DQ3

W#/ VPP /DQ2
Note See Part Number Ordering Information for complete package names and details.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.
64Mb, 3V, Multiple I/O Serial Flash Memory Signal Descriptions

Signal Descriptions

The signal description table below is a comprehensive list of signals for the N25 family devices. All signals listed may not be supported on this device. See Signal Assignments for information specific to this device.

Table 1 Signal Descriptions

Symbol C S#

DQ2 DQ3 RESET#

Type Input

Input and I/O

Output and I/O

Input and I/O

Input and I/O Control Input

Clock Provides the timing of the serial interface. Commands, addresses, or data present at serial data inputs are latched on the rising edge of the clock. Data is shifted out on the falling edge of the clock.

Chip select When S# is HIGH, the device is deselected and DQ1 is at High-Z. When in extended SPI mode, with the device deselected, DQ1 is tri-stated. Unless an internal PROGRAM, ERASE, or WRITE STATUS REGISTER cycle is in progress, the device enters standby power mode not deep power-down mode . Driving S# LOW enables the device, placing it in the active power mode. After power-up, a falling edge on S# is required prior to the start of any command.

Serial data Transfers data serially into the device. It receives command codes, addresses, and the data to be programmed. Values are latched on the rising edge of the clock. DQ0 is used for input/output during the following operations DUAL OUTPUT FAST READ, QUAD OUTPUT FAST READ, DUAL INPUT/OUTPUT FAST READ, and QUAD INPUT/OUTPUT FAST READ. When used for output, data is shifted out on the falling edge of the clock. In DIO-SPI, DQ0 always acts as an input/output. In QIO-SPI, DQ0 always acts as an input/output, with the exception of the PROGRAM or ERASE cycle performed with VPP. The device temporarily enters the extended SPI protocol and then returns to QIO-SPI as soon as VPP goes LOW.

Serial data:Transfers data serially out of the device. Data is shifted out on the falling edge of the clock. DQ1 is used for input/output during the following operations DUAL INPUT FAST PROGRAM, QUAD INPUT FAST PROGRAM, DUAL INPUT EXTENDED FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. When used for input, data is latched on the rising edge of the clock. In DIO-SPI, DQ1 always acts as an input/output. In QIO-SPI, DQ1 always acts as an input/output, with the exception of the PROGRAM or ERASE cycle performed with the enhanced program supply voltage VPP . In this case the device temporarily enters the extended SPI protocol and then returns to QIO-SPI as soon as VPP goes LOW.

DQ2 When in QIO-SPI mode or in extended SPI mode using QUAD FAST READ commands, the signal functions as DQ2, providing input/output. All data input drivers are always enabled except when used as an output. Micron recommends customers drive the data signals normally to avoid unnecessary switching current and float the signals before the memory device drives data on them.

DQ3 When in quad SPI mode or in extended SPI mode using quad FAST READ commands, the signal functions as DQ3, providing input/output. HOLD# is disabled and RESET# is disabled if the device is selected.

RESET This is a hardware RESET# signal. When RESET# is driven HIGH, the memory is in the normal operating mode. When RESET# is driven LOW, the memory enters reset mode and output is High-Z. If RESET# is driven LOW while an internal WRITE, PROGRAM, or ERASE operation is in progress, data may be lost.

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64Mb, 3V, Multiple I/O Serial Flash Memory Signal Descriptions

Table 1 Signal Descriptions Continued

Symbol HOLD#

VCC VSS DNU NC

Type Control Input

Control Input

Power

Power Ground

HOLD Pauses any serial communications with the device without deselecting the device. DQ1 output is High-Z. DQ0 input and the clock are "Don't Care." To enable HOLD, the device must be selected with S# driven LOW. HOLD# is used for input/output during the following operations QUAD OUTPUT FAST READ, QUAD INPUT/OUTPUT FAST READ, QUAD INPUT FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. In QIO-SPI, HOLD# acts as an I/O DQ3 functionality , and the HOLD# functionality is disabled when the device is selected. When the device is deselected S# is HIGH in parts with RESET# functionality, it is possible to reset the device unless this functionality is not disabled by means of dedicated registers bits. The HOLD# functionality can be disabled using bit 4 of the NVCR or bit 4 of the VECR.

Write protect W# can be used as a protection control input or in QIO-SPI operations. When in extended SPI with single or dual commands, the WRITE PROTECT function is selectable by the voltage range applied to the signal. If voltage range is low 0V to VCC , the signal acts as a write protection control input. The memory size protected against PROGRAM or ERASE operations is locked as specified in the status register block protect bits W# is used as an input/output DQ2 functionality during QUAD INPUT FAST READ and QUAD INPUT/OUTPUT FAST READ operations and in QIO-SPI.

Supply voltage If VPP is in the voltage range of VPPH, the signal acts as an additional power supply, as defined in the AC Measurement Conditions table. During QIFP, QIEFP, and QIO-SPI PROGRAM/ERASE operations, it is possible to use the additional VPP power supply to speed up internal operations. However, to enable this functionality, it is necessary to set bit 3 of the VECR to In this case, VPP is used as an I/O until the end of the operation. After the last input data is shifted in, the application should apply VPP voltage to VPP within 200ms to speed up the internal operations. If the VPP voltage is not applied within 200ms, the PROGRAM/ERASE operations start at standard speed. The default value of VECR bit 3 is 1, and the VPP functionality for quad I/O modify operations is disabled.

Device core power supply Source voltage.

Ground Reference for the VCC supply voltage.

Do not use.

No connect.

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64Mb, 3V, Multiple I/O Serial Flash Memory Organization

Memory Organization

Memory Configuration and Block Diagram

Each page of memory can be individually programmed. Bits are programmed from one through zero. The device is subsector, sector, or bulk-erasable, but not page-erasable. Bits are erased from zero through one. The memory is configured as 8,388,608 bytes 8 bits each 128 sectors 64KB each 2048 subsectors 4KB each and 37,768 pages 256 bytes each and 64 OTP bytes are located outside the main memory array.
Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details.

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64Mb, 3V, Multiple I/O Serial Flash Memory Package Dimensions
aaa C NE - 1 x TYP
eee M C A B fff M C

Figure 42 V-PDFN-8 8mm x 6mm MLP8 Package Code F8

A B TYP

TYP/ 1 MAX

TYP Pin 1 ID
aaa C

Pin 1 ID R

TYP 6
2 TYP
bbb C ddd C
Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details.

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64Mb, 3V, Multiple I/O Serial Flash Memory Package Dimensions

Figure 43 T-PBGA-24b05 6mm x 8mm Package Code 12

Seating plane A
54321

Ball A1 ID

A B C 8 D E

Ball A1 ID
Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details.

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64Mb, 3V, Multiple I/O Serial Flash Memory Package Dimensions

Figure 44 T-PBGA-24b05 6mm x 8mm Package Code 14

Seating plane
24X Dimensions apply to solder balls postreflow on SMD ball pads.
5 CTR 8
1 TYP

Ball A1 ID
432 1

A B C D E F

Ball A1 ID
1 TYP 3 CTR 6
Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details.

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64Mb, 3V, Multiple I/O Serial Flash Memory Package Dimensions

Figure 45 SOP2-16 300 mils body width Package Code SF

MIN/ MAX
h x 45°

MIN/ MAX
0° MIN/8° MAX

MIN/ MAX

TYP Z

MIN/ MAX
Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details.

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64Mb, 3V, Multiple I/O Serial Flash Memory Package Dimensions

Figure 46 SOP2-8 208 mils body width Package Code SE

MIN/ MAX

MIN/ MAX

MIN/ MAX

MIN/ MAX

MIN/ MAX

MIN/ MAX MIN/ MAX

MIN/ MAX
0º MIN/ 10º MAX

MIN/ MAX
Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details.

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64Mb, 3V, Multiple I/O Serial Flash Memory Package Dimensions

Figure 47 XF-SCSP-8/2.93mm x 3.5mm Package Code 53
12X Dimensions apply to solder balls postreflow on UBM ball pads.
4321

A B C D E F

Seating plane A

Ball A1 ID
Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details.

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64Mb, 3V, Multiple I/O Serial Flash Memory Part Number Ordering Information
Part Number Ordering Information

Micron Serial NOR Flash devices are available in different configurations and densities. Verify valid part numbers by using Micron’s part catalog search at micron.com. To compare features and specifications by device type, visit micron.com/products. Contact the factory for devices not found.

For more information on how to identify products and top-side marking by the process identification letter, refer to technical note TN-12-24, "Serial Flash Memory Device Marking for the M25P, M25PE, M25PX, and N25Q Product Families."

Table 39 Part Number Information

Part Number Category Device type Density Technology Feature set

Operating voltage Block structure Package RoHS-compliant

Temperature and test flow

Security features Shipping material

Category Details

N25Q = Serial NOR Flash memory, Multiple Input/Output Single, Dual, Quad I/O , XIP
064 = 64Mb

A = 65nm
1 = Byte addressability HOLD pin Micron XIP
2 = Byte addressability HOLD pin Basic XIP
3 = Byte addressability RST# pin Micron XIP
4 = Byte addressability RST# pin Basic XIP
3 = VCC = to 3.6V E = Uniform 64KB and 4KB

F6 = V-PDFN-8 6mm x 5mm MLP8 6mm x 5mm F8 = V-PDFN-8 8mm x 6mm MLP8 8mm x 6mm 12 = T-PBGA-24b05 6mm x 8mm 14 = T-PBGA-24b05 6mm x 8mm, 4x6 ball array SF = SOP2-16 300 mils body width SO16W SE = SOP2-8 208 mils body width SO8W 53 = XF-SCSP-8/2.93mm x 3.5mm XFCSP
4 = IT to +85°C Device tested with standard test flow A = Automotive temperature range to +125°C Device tested with high reliability certified test flow H = IT to +85°C Device tested with high reliability certified test flow
0 = Default

E = Tray F = Tape and reel G = Tube

Note Additional secure options are available upon customer request.

Notes 1

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64Mb, 3V, Multiple I/O Serial Flash Memory Part Number Ordering Information

Table 40 Package Details

Micron SPI and JEDEC

Package Name

V-PDFN-8 6mm x 5mm

V-PDFN-8 8mm x 6mm

T-PBGA24b05/6mm x

T-PBGA24b05/6mm x
8mm 4x6 ball array

SOP2- 16/ 300 mil

SOP2- 8/ 208 mil

XF-SCSP-8/ 2.93mm x
3.5mm

Shortened Package Name

DFN/6mm x 5mm

DFN/8mm x 6mm

TBGA 24

Package Description

Very thin, plastic small-outline, 8 terminal pads no leads , 6mm x 5mm

Very thin, plastic small outline, 8 terminal pads no leads , 8mm x 6mm

Thin plastic ball grid array, 24 balls, 6mm x 8mm

TBGA 24

Thin plastic ball grid array, 24 balls, 6mm x 8mm, 4x6 ball array

SO16W SO8W XFCSP

Small-outline integrated circuit, 16 pins, wide 300 mil

Small-outline integrated circuit, 8-pins, wide 208 mil

Wafer level, chip-scale package, 12 balls 8 active balls , 2.93mm x 3.5mm x 0.41mm

M25P M45PE Symbol

MF MW

N25Q Symbol

M25P M45PE Package Names

MLP8, DFN8, VDFPN8, VFQFPN8

MLP8, VDFPN8

Alternate Package Name V-PSON1-8/6mm
x 5mm, VSON

V-PSON1-8/8mm x 6mm, VSON

TBGA24 6mm x

TBGA24 6mm x
4x6 ball array

SO16 wide 300 SOIC-16/300 mil,
mil body width SOP 16L 300 mil
• Updated HOLD# description in Signal Description table
• Updated SOP2-8 208 mils body width - Package Code SE in Package Dimensions
• Updated the READ ID Operation figure in READ ID Operations
• Updated ERASE Operations
• Added link to part number chart in Part Number Ordering Information
• Updated part numbers in Features
• Updated tBE from 250 to 120 in AC Characteristics and Operating Conditions.
• Updated part numbers
• Updated tSSE specification in AC Reset Conditions table
• Micron rebrand

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.
• In Ordering Information, changed the following E = Uniform 4KB subsector erase and Uniform 64KB sector erase
• Updated package information
• Initial release
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel 208-368-4000 Sales inquiries 800-932-4992

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This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived N25Q064A13E5340FTR Datasheet file may be downloaded here without warranties.

Datasheet ID: N25Q064A13E5340FTR 648534