FDG6313N

FDG6313N Datasheet

FDG6313N Dual N-Channel, Digital FET

Part	Datasheet
FDG6313N	FDG6313N (pdf)

PDF Datasheet Preview
April 2002 FDG6313N Dual N-Channel, Digital FET These dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. 25 V, A continuous, A peak. RDS ON = VGS= V, RDS ON VGS= V. Very low level gate drive requirements allowing direct operation in 3 V circuits VGS th < V . Gate-Source Zener for ESD ruggedness >6kV Human Body Model . Compact industry standard SC70-6 surface mount package. SC70-6 SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 S2 G2 D1 SC70-6 D2 G1 S1 1 or 4 * 2 or 5 3 or 6 * The pinouts are symmetrical pin 1 and 4 are interchangeable. Units inside the carrier can be of either orientation and will not affect the functionality of the device. Absolute Maximum Ratings TA = 25°C unless otherwise noted Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage Drain/Output Current - Continuous - Pulsed PD TJ,TSTG ESD Maximum Power Dissipation Note 1 Operating and Storage Temperature Range Electrostatic Discharge Rating MIL-STD-883D Human Body Model 100 pF / 1500 THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient FDG6313N 25 - to +8 -55 to 150 6 or 3 5 or 2

PDF Datasheet Preview

April 2002

FDG6313N Dual N-Channel, Digital FET

These dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs.
25 V, A continuous, A peak. RDS ON = VGS= V,

RDS ON VGS= V.

Very low level gate drive requirements allowing direct operation in 3 V circuits VGS th < V .

Gate-Source Zener for ESD ruggedness >6kV Human Body Model .

Compact industry standard SC70-6 surface mount package.

SC70-6

SOT-23

SuperSOTTM-6

SuperSOTTM-8

SO-8

SOT-223

S2 G2 D1

SC70-6

D2 G1 S1
1 or 4 *
2 or 5 3 or 6
* The pinouts are symmetrical pin 1 and 4 are interchangeable.

Units inside the carrier can be of either orientation and will not affect the functionality of the device.

Absolute Maximum Ratings TA = 25°C unless otherwise noted

Symbol Parameter

VDSS

Drain-Source Voltage

VGSS

Gate-Source Voltage

Drain/Output Current - Continuous
- Pulsed

PD TJ,TSTG ESD

Maximum Power Dissipation

Note 1

Operating and Storage Temperature Range

Electrostatic Discharge Rating MIL-STD-883D Human Body Model 100 pF / 1500

THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient

FDG6313N 25
- to +8
-55 to 150
6 or 3
5 or 2

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Datasheet ID: FDG6313N 514170