DM74S163N

DM74S163N Datasheet

DM74S161<br>• DM74S163 Synchronous 4-Bit Binary Counters

Part	Datasheet
DM74S163N	DM74S163N (pdf)

Related Parts	Information
DM74S161N	DM74S161N

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DM74S161 • DM74S163 Synchronous 4-Bit Binary Counters DM74S161 • DM74S163 Synchronous 4-Bit Binary Counters These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. They are 4-bit binary counters. The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous ripple clock counters. A buffered clock input triggers the four flip-flops on the rising positivegoing edge of the clock input waveform. These counters are fully programmable that is, the outputs may be preset to either level. As presetting is synchronous, setting up a LOW level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable input. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs P and T must be HIGH to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a HIGH-level output pulse with a duration approximately equal to the HIGH-level portion of the QA output. This HIGH-level overflow ripple carry pulse can be used to enable successive cascaded stages. s Synchronously programmable s Internal look-ahead for fast counting s Carry output for n-bit cascading s Synchronous counting s Load control line s Diode-clamped inputs Ordering Code: Order Number DM74S161N DM74S163N Package Number Package Description N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Connection Diagram 2000 Fairchild Semiconductor Corporation DS006471 DM74S161 • DM74S163 Logic Diagram DM74S161 • DM74S163 DM74S161 • DM74S163 Timing Diagram Sequence Clear outputs to zero Preset to binary twelve Count to thirteen, fourteen, fifteen, zero, one and two Inhibit DM74S161 • DM74S163 Parameter Measurement Information Switching Time Waveforms Note A:The input pulses are supplied by generators having the following characteristics PRR 1 MHz, duty cycle 50%, ZOUT For DM74S161/163, tr ns, tf ns. Vary PRR to measure fMAX. Note B Outputs QDand carry are tested at tn + 16 for DM74S161, SM74S163 where tn is the bit time when all outputs are LOW Note C VREF = 1.5V. Switching Time Waveforms Note A The input pulses are supplied by generators having the following characteristics PRR 1 MHz, duty cycle 50%, ZOUT tr ns, tf ns. Vary PRR to measure fMAX. Note B Enable P and enable T setup times are measured at tn + Note C:VREF = 1.5V. DM74S161 • DM74S163 Absolute Maximum Ratings Note 1 Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0°C to +70°C −65°C to +150°C Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current fCLK Clock Frequency Note 2 Clock Frequency Note 3 Pulse Width Note 2

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DM74S161
• DM74S163 Synchronous 4-Bit Binary Counters

DM74S161
• DM74S163 Synchronous 4-Bit Binary Counters

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. They are 4-bit binary counters. The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous ripple clock counters. A buffered clock input triggers the four flip-flops on the rising positivegoing edge of the clock input waveform.

These counters are fully programmable that is, the outputs may be preset to either level. As presetting is synchronous, setting up a LOW level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable input.

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs P and T must be HIGH to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a HIGH-level output pulse with a duration approximately equal to the HIGH-level portion of the QA output. This HIGH-level overflow ripple carry pulse can be used to enable successive cascaded stages.
s Synchronously programmable s Internal look-ahead for fast counting s Carry output for n-bit cascading s Synchronous counting s Load control line s Diode-clamped inputs
Ordering Code:

Order Number DM74S161N DM74S163N

Package Number

Package Description

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

Connection Diagram
2000 Fairchild Semiconductor Corporation DS006471

DM74S161
• DM74S163

Logic Diagram

DM74S161
• DM74S163

DM74S161
• DM74S163

Timing Diagram

Sequence Clear outputs to zero Preset to binary twelve Count to thirteen, fourteen, fifteen, zero, one and two Inhibit

DM74S161
• DM74S163

Parameter Measurement Information

Switching Time Waveforms

Note A:The input pulses are supplied by generators having the following characteristics PRR 1 MHz, duty cycle 50%, ZOUT For DM74S161/163, tr ns, tf ns. Vary PRR to measure fMAX.

Note B Outputs QDand carry are tested at tn + 16 for DM74S161, SM74S163 where tn is the bit time when all outputs are LOW Note C VREF = 1.5V.

Switching Time Waveforms

Note A The input pulses are supplied by generators having the following characteristics PRR 1 MHz, duty cycle 50%, ZOUT tr ns, tf ns. Vary PRR to measure fMAX.

Note B Enable P and enable T setup times are measured at tn +

Note C:VREF = 1.5V.

DM74S161
• DM74S163

Absolute Maximum Ratings Note 1

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range
7V 5.5V 0°C to +70°C −65°C to +150°C

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

Parameter

Supply Voltage

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Current

LOW Level Output Current
fCLK

Clock Frequency Note 2

Clock Frequency Note 3

Pulse Width Note 2

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Datasheet ID: DM74S163N 513833