CD4007CN

CD4007CN Datasheet

CD4007C Dual Complementary Pair Plus Inverter

Part	Datasheet
CD4007CN	CD4007CN (pdf)

Related Parts	Information
CD4007CM	CD4007CM

PDF Datasheet Preview
CD4007C Dual Complementary Pair Plus Inverter CD4007C Dual Complementary Pair Plus Inverter The CD4007C consists of three complementary pairs of Nand P-channel enhancement mode MOS transistors suitable for series/shunt applications. All inputs are protected from static discharge by diode clamps to VDD and VSS. For proper operation the voltages at all pins must be constrained to be between VSS − 0.3V and VDD + 0.3V at all times. s Wide supply voltage range 3.0V to 15V s High noise immunity VCC typ. Ordering Code: Order Number Package Number Package Description CD4007CM M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow CD4007CN N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC Note All P-channel substrates are connected to VDD and all N-channel substrates are connected to VSS. Top View 1999 Fairchild Semiconductor Corporation DS005943.prf CD4007C Absolute Maximum Ratings Note 1 Voltage at Any Pin Operating Temperature Range Storage Temperature Range Power Dissipation PD Dual-In-Line Small Outline VSS −0.3V to VDD +0.3V −40°C to +85°C −65°C to +150°C Operating VDD Range Lead Temperature Soldering, 10 seconds VSS +3.0V to VSS +15V 260°C 700 mW 500 mW Note 1 This device should not be connected to circuits with the power on because high transient voltages may cause permanent damage. DC Electrical Characteristics Parameter Quiescent Device Current Quiescent Device Dissipation Package Output Voltage LOW Level Output Voltage HIGH Level Noise Immunity All inputs Noise Immunity All Inputs Output Drive Current N-Channel Output Drive Current P-Channel Input Current Limits Conditions −40°C +25°C +85°C

PDF Datasheet Preview

CD4007C Dual Complementary Pair Plus Inverter

CD4007C Dual Complementary Pair Plus Inverter

The CD4007C consists of three complementary pairs of Nand P-channel enhancement mode MOS transistors suitable for series/shunt applications. All inputs are protected from static discharge by diode clamps to VDD and VSS.

For proper operation the voltages at all pins must be constrained to be between VSS − 0.3V and VDD + 0.3V at all times.
s Wide supply voltage range 3.0V to 15V s High noise immunity VCC typ.
Ordering Code:

Order Number Package Number

Package Description

CD4007CM

M14A
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow

CD4007CN

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Assignments for DIP and SOIC

Note All P-channel substrates are connected to VDD and all N-channel substrates are connected to VSS.

Top View
1999 Fairchild Semiconductor Corporation DS005943.prf

CD4007C

Absolute Maximum Ratings Note 1

Voltage at Any Pin Operating Temperature Range Storage Temperature Range Power Dissipation PD

Dual-In-Line Small Outline

VSS −0.3V to VDD +0.3V −40°C to +85°C
−65°C to +150°C

Operating VDD Range Lead Temperature

Soldering, 10 seconds

VSS +3.0V to VSS +15V 260°C
700 mW 500 mW

Note 1 This device should not be connected to circuits with the power on because high transient voltages may cause permanent damage.

DC Electrical Characteristics

Parameter

Quiescent Device

Current

Quiescent Device

Dissipation Package

Output Voltage

LOW Level

Output Voltage

HIGH Level

Noise Immunity

All inputs

Noise Immunity

All Inputs

Output Drive Current

N-Channel

Output Drive Current

P-Channel

Input Current

Limits

Conditions
−40°C
+25°C
+85°C

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Datasheet ID: CD4007CN 513545