DM74LS574N

DM74LS574N Datasheet

DM74LS574 Octal D-Type Flip-Flop with 3-STATE Outputs

Part	Datasheet
DM74LS574N	DM74LS574N (pdf)

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DM74LS574 Octal D-Type Flip-Flop with 3-STATE Outputs DM74LS574 Octal D-Type Flip-Flop with 3-STATE Outputs The DM74LS574 is a high speed low power octal flip-flop with a buffered common Clock CP and a buffered common Output Enable OE . The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH Clock CP transition. This device is functionally identical to the DM74LS374 except for the pinouts. Ordering Code: Order Number Package Number Package Description DM74LS574WM M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide DM74LS574N N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram VCC = Pin 20 GND = Pin 10 Truth Table Inputs Dn H L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = High Impedance = HIGH-to-LOW Clock CP transition Outputs 2000 Fairchild Semiconductor Corporation DS009815 DM74LS574 Functional Description The DM74LS574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Outputs Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock CP tran- sition. With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Logic Diagram DM74LS574 Absolute Maximum Ratings Note 1 Supply Voltage Input Voltage Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions VCC VIH VIL IOH IOL TA tS H tS L tH H tH L tW H tW L Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature Setup Time HIGH or LOW Dn to CP Hold Time HIGH or LOW Dn to CP Pulse Width HIGH or LOW Nom 5 0 20 0 15 Electrical Characteristics over recommended operating free air temperature range unless otherwise noted Parameter Conditions Input Clamp Voltage VCC = Min, II = −18 mA HIGH Level Output Voltage VCC = Min, IOH = Max, VIL = Max, VIH = Min LOW Level VCC = Min, IOL = Max,

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DM74LS574 Octal D-Type Flip-Flop with 3-STATE Outputs

DM74LS574

Octal D-Type Flip-Flop with 3-STATE Outputs

The DM74LS574 is a high speed low power octal flip-flop with a buffered common Clock CP and a buffered common Output Enable OE . The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH Clock CP transition. This device is functionally identical to the DM74LS374 except for the pinouts.
Ordering Code:

Order Number Package Number Package Description

DM74LS574WM M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide

DM74LS574N N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagram

VCC = Pin 20 GND = Pin 10

Truth Table

Inputs

Dn H L

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
= High Impedance = HIGH-to-LOW Clock CP transition

Outputs
2000 Fairchild Semiconductor Corporation DS009815

DM74LS574

Functional Description

The DM74LS574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Outputs Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock CP tran-
sition. With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.

Logic Diagram

DM74LS574

Absolute Maximum Ratings Note 1

Supply Voltage

Input Voltage

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range
−65°C to +150°C

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

VCC VIH VIL IOH IOL TA tS H tS L tH H tH L tW H tW L

Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature Setup Time HIGH or LOW Dn to CP Hold Time HIGH or LOW Dn to CP Pulse Width HIGH or LOW

Nom 5
0 20 0 15

Electrical Characteristics
over recommended operating free air temperature range unless otherwise noted

Parameter

Conditions

Input Clamp Voltage

VCC = Min, II = −18 mA

HIGH Level

Output Voltage

VCC = Min, IOH = Max,

VIL = Max, VIH = Min

LOW Level

VCC = Min, IOL = Max,

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Datasheet ID: DM74LS574N 513806