74VCXH16373MTD

74VCXH16373MTD Datasheet

74VCXH16373 Low Voltage 16-Bit Transparent Latch with Bushold

Part	Datasheet
74VCXH16373MTD	74VCXH16373MTD (pdf)

Related Parts	Information
74VCXH16373MTDX	74VCXH16373MTDX

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74VCXH16373 Low Voltage 16-Bit Transparent Latch with Bushold 74VCXH16373 Low Voltage 16-Bit Transparent Latch with Bushold The VCXH16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear to be transparent to the data when the Latch Enable LE is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the outputs are in a high impedance state. The VCXH16373 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The 74VCXH16373 is designed for low voltage 1.2V to 3.6V VCC applications with output compatibility up to 3.6V. The 74VCXH16373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. s 1.2V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminates the need for external pull-up/pull-down resistors s tPD In to On ns max for 3.0V to 3.6V VCC s Static Drive IOH/IOL r24 mA 3.0V VCC s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 mA s ESD performance: Human body model ! 2000V Machine model ! 200V s Also packaged in plastic Fine-Pitch Ball Grid Array FBGA Preliminary Ordering Code: Order Number Package Number Package Description 74VCXH16373G Note 1 Note 2 BGA54A 54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide 74VCXH16373MTD Note 2 MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Note 1 Ordering Code “G” indicates Tray. Note 2 Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol 2005 Fairchild Semiconductor Corporation DS500229 74VCXH16373 Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA Top Thru View Pin Descriptions Pin Names OEn LEn NC Description Output Enable Input Active LOW Latch Enable Input Bushold Inputs Outputs No Connect FBGA Pin Assignments NC OE1 LE1 NC O5 GND I5 O7 GND I7 O9 GND O15 NC OE2 LE2 NC Truth Tables Inputs Outputs Inputs Outputs H HIGH Voltage Level L LOW Voltage Level X Immaterial HIGH or LOW, control inputs may not float Z High Impedance O0 Previous O0 before HIGH-to-LOW of Latch Enable 74VCXH16373 Functional Description The 74VCXH16373 contains sixteen edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable LEn input is HIGH, data on the In enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time Logic Diagram its I input changes. When LEn is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition on LEn. The 3-STATE outputs are controlled by the Output Enable OEn input. When OEn is LOW the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74VCXH16373 Absolute Maximum Ratings Note 3 Supply Voltage VCC DC Input Voltage VI Output Voltage VO Outputs 3-STATED Outputs Active Note 4 DC Input Diode Current IIK VI 0V DC Output Diode Current IOK VO 0V VO ! VCC DC Output Source/Sink Current IOH/IOL DC VCC or GND Current per Supply Pin ICC or GND Storage Temperature Range TSTG to 4.6V to VCC

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74VCXH16373 Low Voltage 16-Bit Transparent Latch with Bushold
74VCXH16373 Low Voltage 16-Bit Transparent Latch with Bushold

The VCXH16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear to be transparent to the data when the Latch Enable LE is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the outputs are in a high impedance state.

The VCXH16373 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level.

The 74VCXH16373 is designed for low voltage 1.2V to 3.6V VCC applications with output compatibility up to 3.6V.

The 74VCXH16373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
s 1.2V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors s tPD In to On
ns max for 3.0V to 3.6V VCC s Static Drive IOH/IOL
r24 mA 3.0V VCC s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 mA s ESD performance:

Human body model ! 2000V Machine model ! 200V s Also packaged in plastic Fine-Pitch Ball Grid Array FBGA Preliminary
Ordering Code:

Order Number Package Number

Package Description
74VCXH16373G Note 1 Note 2

BGA54A
54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide
74VCXH16373MTD Note 2

MTD48
48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Note 1 Ordering Code “G” indicates Tray. Note 2 Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol
2005 Fairchild Semiconductor Corporation DS500229
74VCXH16373

Connection Diagrams

Pin Assignment for TSSOP

Pin Assignment for FBGA Top Thru View

Pin Descriptions

Pin Names

OEn LEn NC

Description Output Enable Input Active LOW

Latch Enable Input Bushold Inputs Outputs No Connect

FBGA Pin Assignments

NC OE1 LE1 NC

O5 GND I5

O7 GND I7

O9 GND

O15 NC OE2 LE2 NC

Truth Tables

Inputs

Outputs

Inputs

Outputs

H HIGH Voltage Level L LOW Voltage Level

X Immaterial HIGH or LOW, control inputs may not float Z High Impedance O0 Previous O0 before HIGH-to-LOW of Latch Enable
74VCXH16373

Functional Description

The 74VCXH16373 contains sixteen edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable LEn input is HIGH, data on the In enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time

Logic Diagram
its I input changes. When LEn is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition on LEn. The 3-STATE outputs are controlled by the Output Enable OEn input. When OEn is LOW the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74VCXH16373

Absolute Maximum Ratings Note 3

Supply Voltage VCC DC Input Voltage VI Output Voltage VO

Outputs 3-STATED

Outputs Active Note 4 DC Input Diode Current IIK VI 0V DC Output Diode Current IOK

VO 0V VO ! VCC DC Output Source/Sink Current

IOH/IOL DC VCC or GND Current per

Supply Pin ICC or GND Storage Temperature Range TSTG
to 4.6V
to VCC

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Datasheet ID: 74VCXH16373MTD 513484