74ALVC162374T

74ALVC162374T Datasheet


74ALVC162374 Low Voltage 16-Bit D-Type Flip-Flop

Part Datasheet
74ALVC162374T 74ALVC162374T 74ALVC162374T (pdf)
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74ALVC162374TX 74ALVC162374TX 74ALVC162374TX
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74ALVC162374 Low Voltage 16-Bit D-Type Flip-Flop
74ALVC162374 Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs and Series Resistors in Outputs

The ALVC162374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock CP and output enable OE are common to each byte and can be shorted together for full 16-bit operation.

The ALVC162374 is also designed with series resistors in the outputs. This design reduces line noise in applications such as memory address drivers, clock drivers and bus transceivers/transmitters.

The 74ALVC162374 is designed for low voltage 1.65V to 3.6V VCC applications with I/O compatibility up to 3.6V.

The 74ALVC162374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
s VCC supply operation s 3.6V tolerant inputs and outputs s series resistors in outputs s tPD CLK to On
ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal Note 1 s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance Human body model > 2000V Machine model > 200V

Note 1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:

Order Number Package Number

Package Descriptions
74ALVC162374T

MTD48
48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Pin Descriptions

Pin Names

OEn CPn

Description Output Enable Input Active LOW Clock Pulse Input Inputs Outputs
2001 Fairchild Semiconductor Corporation DS500688
74ALVC162374

Connection Diagram

Truth Tables

Inputs

Outputs

OE1 L

Inputs

Outputs

OE2 L

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, inputs may not float Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of CP

Functional Description

The 74ALVC162374 consists of sixteen edge-triggered flipflops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each clock has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-

Logic Diagram
flop will store the state of their individual I inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CPn transition. With the Output Enable OEn LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operations of the OEn input does not affect the state of the flip-flops.

Byte 1 0:7

Byte 2 8:15

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ALVC162374

Absolute Maximum Ratings Note 2

Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 3 DC Input Diode Current IIK

VI < 0V DC Output Diode Current IOK

VO < 0V DC Output Source/Sink Current

IOH/IOL DC VCC or GND Current per

Supply Pin ICC or GND Storage Temperature Range TSTG
−0.5V to +4.6V −0.5V to 4.6V
−0.5V to VCC +0.5V
−50 mA
−50 mA
±50 mA
±100 mA −65°C to +150°C

Recommended Operating Conditions Note 4

Power Supply

Operating
1.65V to 3.6V
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Datasheet ID: 74ALVC162374T 513229