74VCX132 Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and Outputs
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74VCX132MX (pdf) |
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74VCX132BQX |
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74VCX132MTCX |
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74VCX132MTC |
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74VCX132M |
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74VCX132 Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and Outputs 74VCX132 Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and Outputs The VCX132 contains four 2-input NAND gates with Schmitt Trigger Inputs. The pin configuration and function are the same as the VCX00 except the inputs have hysteresis between the positive-going and negative-going input thresholds. This hysteresis is useful for transforming slowly switching input signals into sharply defined, jitter-free output signals. This product should be used where noise margin greater than that of conventional gates is required. The VCX132 is designed for low voltage 1.4V to 3.6V VCC applications with I/O compatibility up to 3.6V. This product is fabricated with an advanced CMOS technology to achieve high-speed operation while maintaining low CMOS power dissipation. s 1.4V to 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD ns max for 3.0V to 3.6V VCC s Power-off high impedance inputs and outputs s Static Drive IOH/IOL r24 mA 3.0V VCC s Uses patented Quiet noise/EMI reduction circuitry s Latchup performance exceeds JEDEC 78 conditions s ESD performance: Human body model ! 2000V Machine model ! 250V s Leadless Pb-Free DQFN package Ordering Code: Order Number Package Number Package Description 74VCX132M M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74VCX132BQX Note 1 MLP014A Pb-Free 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads DQFN , JEDEC MO-241, x 3.0mm 74VCX132MTC MTC14 14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1 DQFN package available in Tape and Reel only. Quiet is a trademark of Fairchild Semiconductor Corporation. 2005 Fairchild Semiconductor Corporation DS500164 74VCX132 Logic Diagram Connection Diagrams Pin Assignments for SOIC and TSSOP Pin Descriptions Pin Name An, Bn On Description Inputs Outputs Pad Assignments for DQFN Top View 74VCX132 Absolute Maximum Ratings Note 2 Supply Voltage VCC DC Input Voltage VI DC Output Voltage VO HIGH or LOW State Note 3 VCC 0V DC Input Diode Current IIK VI 0V DC Output Diode Current IOK VO 0V VO ! VCC DC Output Source/Sink Current IOH/IOL DC VCC or Ground Current per Supply Pin ICC or Ground Storage Temperature TSTG to 4.6V to VCC 0.5V to r50 mA r100 mA to Recommended Operating Conditions Note 4 Power Supply Operating Input Voltage Output Voltage VO HIGH or LOW State Output Current in IOH/IOL VCC 3.0V to 3.6V VCC 2.3V to 2.7V VCC 1.65V to 2.3V VCC 1.4V to 1.6V Free Air Operating Temperature TA 1.4V to 3.6V to 3.6V 0V to VCC r24 mA r18 mA r6 mA r2 mA to Note 2 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 3 IO Absolute Maximum Rating must be observed. Note 4 Floating or unused inputs must be held HIGH or LOW. DC Electrical Characteristics Parameter HIGH Level Input Voltage Conditions LOW Level Input Voltage |
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