74LVT374MTCX

74LVT374MTCX Datasheet

74LVT374, 74LVTH374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs

Part	Datasheet
74LVT374MTCX	74LVT374MTCX (pdf)

Related Parts	Information
74LVT374SJX	74LVT374SJX
74LVT374SJ	74LVT374SJ
74LVT374WM	74LVT374WM
74LVT374WMX	74LVT374WMX
74LVT374MTC	74LVT374MTC

PDF Datasheet Preview
74LVT374, 74LVTH374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs January 2008 74LVT374, 74LVTH374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs • Input and output interface capability to systems at 5V VCC • Bus-Hold data inputs eliminate the need for external pull-up resistors to hold unused inputs 74LVTH374 , also available without bushold feature 74LVT374 • Live insertion/extraction permitted • Power Up/Down high impedance provides glitch-free bus loading • Outputs source/sink • Functionally compatible with the 74 series 374 • Latch-up performance exceeds 500mA • ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V The LVT374 and LVTH374 are high-speed, low-power octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock CP and Output Enable OE are common to all flip-flops. The LVTH374 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These octal flip-flops are designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT374 and LVTH374 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. Ordering Information Order Number Package Number Package Description 74LVT374WM 74LVT374SJ 74LVT374MTC 74LVTH374WM 74LVTH374SJ 74LVTH374MTC M20B M20D MTC20 M20B M20D MTC20 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC J-STD-020B standard. 74LVT374, 74LVTH374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs Connection Diagram Logic Symbols IEEE/IEC Pin Description Pin Names CP OE Description Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs Functional Description The LVT374 and LVTH374 consist of eight edgetriggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flipflops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOWto-HIGH Clock CP transition. With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Truth Table Inputs Outputs On H L Oo Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition Oo = Previous Oo before HIGH-to-LOW of CP 1999 Fairchild Semiconductor Corporation 74LVT374, 74LVTH374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 1999 Fairchild Semiconductor Corporation 74LVT374, 74LVTH374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter Supply Voltage DC Input Voltage DC Output Voltage Output in 3-STATE Output in HIGH or LOW State 1 DC Input Diode Current, VI < GND DC Output Diode Current, VO < GND DC Output Current, VO > VCC Output at HIGH State Output at LOW State ICC IGND TSTG DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Note IO Absolute Maximum Rating must be observed. Rating to +4.6V to +7.0V to +7.0V to +7.0V 64mA 128mA ±64mA ±128mA to +150°C

PDF Datasheet Preview

74LVT374, 74LVTH374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs

January 2008
74LVT374, 74LVTH374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
• Input and output interface capability to systems at 5V VCC
• Bus-Hold data inputs eliminate the need for external pull-up resistors to hold unused inputs 74LVTH374 , also available without bushold feature 74LVT374
• Live insertion/extraction permitted
• Power Up/Down high impedance provides glitch-free
bus loading
• Outputs source/sink
• Functionally compatible with the 74 series 374
• Latch-up performance exceeds 500mA
• ESD performance:

Human-body model > 2000V Machine model > 200V Charged-device model > 1000V

The LVT374 and LVTH374 are high-speed, low-power octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock CP and Output Enable OE are common to all flip-flops.

The LVTH374 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.

These octal flip-flops are designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT374 and LVTH374 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.
Ordering Information

Order Number

Package Number

Package Description
74LVT374WM 74LVT374SJ 74LVT374MTC
74LVTH374WM 74LVTH374SJ 74LVTH374MTC

M20B M20D MTC20

M20B M20D MTC20
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC J-STD-020B standard.
74LVT374, 74LVTH374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs

Connection Diagram

Logic Symbols

IEEE/IEC

Pin Description

Pin Names CP OE

Description Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs

Functional Description

The LVT374 and LVTH374 consist of eight edgetriggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flipflops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOWto-HIGH Clock CP transition. With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.

Truth Table

Inputs

Outputs On H L Oo Z

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
= LOW-to-HIGH Transition Oo = Previous Oo before HIGH-to-LOW of CP
1999 Fairchild Semiconductor Corporation
74LVT374, 74LVTH374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
1999 Fairchild Semiconductor Corporation
74LVT374, 74LVTH374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Parameter

Supply Voltage

DC Input Voltage

DC Output Voltage

Output in 3-STATE

Output in HIGH or LOW State 1

DC Input Diode Current, VI < GND

DC Output Diode Current, VO < GND

DC Output Current, VO > VCC

Output at HIGH State

Output at LOW State

ICC IGND TSTG

DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature

Note IO Absolute Maximum Rating must be observed.

Rating to +4.6V to +7.0V
to +7.0V to +7.0V
64mA 128mA ±64mA ±128mA to +150°C

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Datasheet ID: 74LVT374MTCX 513440