74LCX32245 Low Voltage 32-Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs
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74LCX32245G (pdf) |
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74LCX32245GX |
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74LCX32245 Low Voltage 32-Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs 74LCX32245 Low Voltage 32-Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs The LCX32245 contains thirty-two non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is designed for low voltage 2.5V or 3.3V VCC applications with capability of interfacing to a 5V signal environment. The device is byte controlled. Each byte has separate control inputs which could be shorted together for full 32-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. The LCX32245 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. s 5V tolerant inputs and outputs s VCC specifications provided s ns tPD max VCC = 3.3V , 20 µA ICC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal Note 1 s ±24 mA output drive VCC = 3.0V s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human body model > 2000V Machine model > 200V s Packaged in plastic Fine-Pitch Ball Grid Array FBGA Note 1 To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74LCX32245G Note 2 Note 3 BGA96A 96-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide Note 2 Ordering code “G” indicates Trays. Note 3 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol 2002 Fairchild Semiconductor Corporation DS500428 74LCX32245 Connection Diagram Top Thru View Truth Tables Inputs T/R1 Outputs Bus Data to Bus Data to Bus HIGH Z State on Pin Descriptions Pin Names OEn T/Rn Output Enable Input Active LOW Transmit/Receive Input Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs FBGA Pin Assignments B0 T/R1 OE1 A0 B2 GND A2 B6 GND A6 B8 GND A8 B11 B10 VCC A10 A11 B13 B12 GND A12 A13 B14 B15 T/R2 OE2 A15 A14 B17 B16 T/R3 OE3 A16 A17 B19 B18 GND A18 A19 B21 B20 VCC A20 A21 B23 B22 GND A22 A23 B25 B24 GND A24 A25 B27 B26 VCC A26 A27 B29 B28 GND A28 A29 B30 B31 T/R4 OE4 A31 A30 Inputs OE2 L H T/R2 L H X Outputs Bus Data to Bus Data to Bus HIGH Z State on Inputs T/R3 H = HIGH Voltage Level L = LOW Voltage Level Outputs Bus Data to Bus Data to Bus HIGH Z State on |
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