CY7C1061GN30-10ZSXIT

CY7C1061GN30-10ZSXIT Datasheet

CY7C1061GN30

Part	Datasheet
CY7C1061GN30-10ZSXIT	CY7C1061GN30-10ZSXIT (pdf)

Related Parts	Information
CY7C1061GN30-10BVXI	CY7C1061GN30-10BVXI
CY7C1061GN30-10BVXIT	CY7C1061GN30-10BVXIT
CY7C1061GN30-10ZSXI	CY7C1061GN30-10ZSXI

PDF Datasheet Preview
CY7C1061GN30 16-Mbit 1 M words x 16 bit Static RAM 16-Mbit 1 M words x 16 bit Static RAM • High speed tAA = 10 ns • Low active power ICC = 90 mA at 100 MHz • Low CMOS standby current ISB2 = 20 mA typ • Operating voltages of V to V • V data retention • Automatic power down when deselected • TTL compatible inputs and outputs • Easy memory expansion with CE1 and CE2 features • Available in Pb-free 54-pin TSOP II, and 48-ball VFBGA packages • Offered in dual Chip Enable options Functional Description The CY7C1061GN30 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. To write to the device, take Chip Enables CE1 LOW and CE2 HIGH and Write Enable WE input LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O0 through I/O7 , is written into the location specified on the address pins A0 through A19 . If Byte High Enable BHE is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A19 . To read from the device, take Chip Enables CE1 LOW and CE2 HIGH and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory appears on I/O8 to I/O15. See Truth Table on page 12 for a complete description of Read and Write modes. The input or output pins I/O0 through I/O15 are placed in a high impedance state when the device is deselected CE1 HIGH/CE2 LOW , the outputs are disabled OE HIGH , the BHE and BLE are disabled BHE, BLE HIGH , or during a write operation CE1 LOW, CE2 HIGH, and WE LOW . Logic Block Diagram A0 A1 A2 AA34 AA56 AAA789 INPUT BUFFER 1M x 16 ARRAY COLUMN DECODER ROW DECODER SENSE AMPS I/O0 I/O7 I/O8 I/O15 AA1189 13 14 AAA111102 • San Jose, CA 95134-1709 • 408-943-2600 CY7C1061GN30 Contents Selection Guide 3 Pin Configurations 3 Maximum Ratings 5 Operating Range 5 DC Electrical Characteristics 5 Capacitance 6 Thermal Resistance 6 AC Test Loads and Waveforms 6 Data Retention Characteristics 7 Over the Operating Range 7 Data Retention Waveform 7 AC Switching Characteristics 8 Switching Waveforms 9 Truth Table 12 Ordering Information 13 Ordering Code Definitions 13 Package Diagrams 14 Acronyms 16 Document Conventions 16 Units of Measure 16 Document History Page 17 Sales, Solutions, and Legal Information 18 Worldwide Sales and Design Support 18 Products 18 Solutions 18 Cypress Developer Community 18 Technical Support 18 Page 2 of 18 CY7C1061GN30 Selection Guide Maximum access time Maximum operating current Maximum CMOS standby current Pin Configurations Figure 48-ball VFBGA 8 x 1 mm Dual Chip Enable pinout Top View [1] BLE OE A0 A1 A2 CE2 I/O8 BHE A3 A4 CE1 I/O0 I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 VCC VCC I/O12 NC A16 I/O4 VSS I/O14 I/O13 A14 A15 I/O5 I/O6 I/O15 NC A12 A13 WE I/O7 G A18 A8 A9 A10 A11 A19 Unit Note NC pins are not connected internally to the die. Page 3 of 18 CY7C1061GN30 Pin Configurations continued Figure 54-pin TSOP II x mm pinout Top View [2] I/O12 I/O13 I/O14 I/O15 BHE 12 WE 15 CE2 16 I/O0 I/O1 24 I/O2 25 I/O3 27 I/O11 I/O10 I/O9 I/O8 I/O7 Ordering Information Speed ns Ordering Code 10 CY7C1061GN30-10ZSXI CY7C1061GN30-10BVXI Package Diagram Package Type 51-85160 54-pin TSOP II x mm Pb-free 51-85150 48-ball VFBGA 6 x 8 x mm Pb-free Dual Chip Enable Operating Range Industrial Ordering Code Definitions CY 7 C 1 06 1 G N 30 - 10 XX X I Temperature Range I = Industrial Pb-free Package Type XX = ZS or BV ZS = 54-pin TSOP II BV = 48-ball VFBGA Dual Chip Enable Speed 10 ns Voltage Range 30 = V to V N = No ECC Process Technology G = 65 nm Technology Data Width 1 = x 16-bits Density 06 = 16-Mbit density Family Code 1 = Fast Asynchronous SRAM family Technology Code C = CMOS Marketing Code 7 = SRAM Company ID CY = Cypress Page 13 of 18 CY7C1061GN30 Package Diagrams Figure 54-pin TSOP II x mm Z54-II Package Outline, 51-85160 51-85160 E Page 14 of 18 CY7C1061GN30 Package Diagrams continued Figure 48-ball VFBGA 6 x 8 x mm BV48/BZ48 Package Outline, 51-85150 51-85150 H Page 15 of 18 Acronyms Acronym Byte High Enable Byte Low Enable Chip Enable CMOS Complementary Metal Oxide Semiconductor Input/Output Output Enable SRAM Static Random Access Memory TSOP Thin Small Outline Package Transistor-Transistor Logic VFBGA Very Fine-Pitch Ball Grid Array Write Enable CY7C1061GN30 Document Conventions Units of Measure Symbol °C MHz mA mm ns % pF V W Unit of Measure degree Celsius megahertz microampere microsecond milliampere millimeter nanosecond ohm percent picofarad volt watt Page 16 of 18 CY7C1061GN30 Document History Page Document Title CY7C1061GN30, 16-Mbit 1 M words x 16 bit Static RAM Document Number 001-93680 ECN No. Orig. of Submission Updated details in “Test Conditions” column of VOH and VOL parameters. Updated Ordering Information: No change in part numbers. Replaced “51-85178” with “51-85150” in “Package Diagram” column. Replaced “8 x 1 mm” with “6 x 8 x mm” in “Package Type” column. Updated Package Diagrams: Removed spec 51-85178 C. Added spec 51-85150 H. Updated to new template. Page 17 of 18 CY7C1061GN30 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Solutions Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 4 \| PSoC 5LP Cypress Developer Community \| Forums \| Blogs \| Video \| Training Technical Support cypress.com/go/support USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 18 of 18

PDF Datasheet Preview

CY7C1061GN30
16-Mbit 1 M words x 16 bit Static RAM
16-Mbit 1 M words x 16 bit Static RAM
• High speed tAA = 10 ns
• Low active power ICC = 90 mA at 100 MHz
• Low CMOS standby current ISB2 = 20 mA typ
• Operating voltages of V to V
• V data retention
• Automatic power down when deselected
• TTL compatible inputs and outputs
• Easy memory expansion with CE1 and CE2 features
• Available in Pb-free 54-pin TSOP II, and 48-ball VFBGA
packages
• Offered in dual Chip Enable options

Functional Description

The CY7C1061GN30 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. To write to the device, take Chip Enables CE1 LOW and CE2 HIGH and Write Enable WE input LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O0 through I/O7 , is written into the location specified on the address pins A0 through A19 . If Byte High Enable BHE is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A19 . To read from the device, take Chip Enables CE1 LOW and CE2 HIGH and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory appears on I/O8 to I/O15. See Truth Table on page 12 for a complete description of Read and Write modes. The input or output pins I/O0 through I/O15 are placed in a high impedance state when the device is deselected CE1 HIGH/CE2 LOW , the outputs are disabled OE HIGH , the BHE and BLE are disabled BHE, BLE HIGH , or during a write operation CE1 LOW, CE2 HIGH, and WE LOW .

Logic Block Diagram

A0 A1 A2 AA34 AA56 AAA789

INPUT BUFFER
1M x 16 ARRAY

COLUMN DECODER

ROW DECODER SENSE AMPS

I/O0 I/O7 I/O8 I/O15

AA1189
13 14

AAA111102
• San Jose, CA 95134-1709
• 408-943-2600

CY7C1061GN30

Contents

Selection Guide 3 Pin Configurations 3 Maximum Ratings 5 Operating Range 5 DC Electrical Characteristics 5 Capacitance 6 Thermal Resistance 6 AC Test Loads and Waveforms 6 Data Retention Characteristics 7 Over the Operating Range 7 Data Retention Waveform 7 AC Switching Characteristics 8 Switching Waveforms 9 Truth Table 12
Ordering Information 13 Ordering Code Definitions 13

Package Diagrams 14 Acronyms 16 Document Conventions 16

Units of Measure 16 Document History Page 17 Sales, Solutions, and Legal Information 18

Worldwide Sales and Design Support 18 Products 18 Solutions 18 Cypress Developer Community 18 Technical Support 18

Page 2 of 18

CY7C1061GN30

Selection Guide

Maximum access time Maximum operating current Maximum CMOS standby current

Pin Configurations

Figure 48-ball VFBGA 8 x 1 mm Dual Chip Enable pinout Top View [1]

BLE OE A0 A1 A2 CE2

I/O8 BHE A3 A4 CE1 I/O0

I/O9 I/O10 A5 A6 I/O1 I/O2 C

VSS I/O11 A17 A7 I/O3 VCC

VCC I/O12 NC A16 I/O4 VSS

I/O14 I/O13 A14 A15 I/O5 I/O6

I/O15 NC A12 A13 WE I/O7 G

A18 A8

A9 A10 A11 A19

Unit

Note NC pins are not connected internally to the die.

Page 3 of 18

CY7C1061GN30

Pin Configurations continued

Figure 54-pin TSOP II x mm pinout Top View [2]

I/O12

I/O13

I/O14

I/O15

BHE 12

WE 15

CE2 16

I/O0

I/O1 24

I/O2 25

I/O3 27

I/O11

I/O10

I/O9

I/O8

I/O7
Ordering Information

Speed ns
Ordering Code
10 CY7C1061GN30-10ZSXI

CY7C1061GN30-10BVXI

Package Diagram

Package Type
51-85160 54-pin TSOP II x mm Pb-free
51-85150 48-ball VFBGA 6 x 8 x mm Pb-free Dual Chip Enable

Operating Range Industrial
Ordering Code Definitions CY 7 C 1 06 1 G N 30 - 10 XX X I

Temperature Range I = Industrial Pb-free Package Type XX = ZS or BV ZS = 54-pin TSOP II BV = 48-ball VFBGA Dual Chip Enable Speed 10 ns Voltage Range 30 = V to V N = No ECC Process Technology G = 65 nm Technology Data Width 1 = x 16-bits Density 06 = 16-Mbit density Family Code 1 = Fast Asynchronous SRAM family Technology Code C = CMOS Marketing Code 7 = SRAM Company ID CY = Cypress

Page 13 of 18

CY7C1061GN30

Package Diagrams

Figure 54-pin TSOP II x mm Z54-II Package Outline, 51-85160
51-85160 *E

Page 14 of 18

CY7C1061GN30

Package Diagrams continued

Figure 48-ball VFBGA 6 x 8 x mm BV48/BZ48 Package Outline, 51-85150
51-85150 *H

Page 15 of 18

Acronyms

Acronym

Byte High Enable

Byte Low Enable

Chip Enable

CMOS

Complementary Metal Oxide Semiconductor

Input/Output

Output Enable

SRAM

Static Random Access Memory

TSOP

Thin Small Outline Package

Transistor-Transistor Logic

VFBGA Very Fine-Pitch Ball Grid Array

Write Enable

CY7C1061GN30

Document Conventions

Units of Measure

Symbol °C MHz mA mm ns
% pF V W

Unit of Measure degree Celsius megahertz microampere microsecond milliampere millimeter nanosecond ohm percent picofarad volt watt

Page 16 of 18

CY7C1061GN30

Document History Page

Document Title CY7C1061GN30, 16-Mbit 1 M words x 16 bit Static RAM Document Number 001-93680

ECN No.

Orig. of Submission
Updated details in “Test Conditions” column of VOH and VOL parameters. Updated Ordering Information:

No change in part numbers.

Replaced “51-85178” with “51-85150” in “Package Diagram” column.

Replaced “8 x 1 mm” with “6 x 8 x mm” in “Package Type” column.

Updated Package Diagrams:

Removed spec 51-85178 *C.

Added spec 51-85150 *H.

Updated to new template.

Page 17 of 18

CY7C1061GN30

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products

Solutions

Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Cypress Developer Community | Forums | Blogs | Video | Training

Technical Support cypress.com/go/support

USB Controllers
cypress.com/go/USB

Wireless/RF
cypress.com/go/wireless

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 18 of 18

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1061GN30-10ZSXIT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1061GN30-10ZSXIT 507911