AT45DB642-TC

AT45DB642-TC Datasheet


The AT45DB642 is a 2.7-volt only, dual-interface Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. The dual-interface of the AT45DB642 allows a dedicated serial interface to be connected to a DSP and a dedicated parallel interface to be connected to a microcontroller or vice versa.

Part Datasheet
AT45DB642-TC AT45DB642-TC AT45DB642-TC (pdf)
Related Parts Information
AT45DB642-TI AT45DB642-TI AT45DB642-TI
PDF Datasheet Preview
• Single 2.7V - 3.6V Supply
• Dual-interface Architecture

Dedicated Serial Interface SPI Modes 0 and 3 Compatible Dedicated Parallel I/O Interface Optional Use
• Page Program Operation Single Cycle Reprogram Erase and Program 8192 Pages 1056 Bytes/Page Main Memory
• Supports Page and Block Erase Operations
• Two 1056-byte SRAM Data Buffers Allows Receiving of Data while Reprogramming the Flash Array
• Continuous Read Capability through Entire Array Ideal for Code Shadowing Applications
• Low-power Dissipation 4 mA Active Read Current Typical 2 µA CMOS Standby Current Typical
• 20 MHz Maximum Clock Frequency Serial Interface
• 5 MHz Maximum Clock Frequency Parallel Interface
• Hardware Data Protection
• Commercial and Industrial Temperature Ranges

The AT45DB642 is a 2.7-volt only, dual-interface Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. The dual-interface of the AT45DB642 allows a dedicated serial interface to be connected to a DSP and a dedicated parallel interface to be connected to a microcontroller or vice versa.

Pin Configurations

Pin Name CS SCK/CLK SI SO I/O7 - I/O0 WP RESET RDY/BUSY SER/PAR

Function Chip Select Serial Clock/Clock Serial Input Serial Output Parallel Input/Output Hardware Page Write Protect Pin Chip Reset Ready/Busy Serial/Parallel Interface Control

DataFlash Card 1

TSOP Top View Type 1

NC 1 NC 2 RDY/BUSY 3 RESET 4 WP 5 NC 6 NC 7 NC 8 VCC 9 GND 10 NC 11 NC 12 NC 13 NC 14 CS 15 SCK/CLK 16 SI* 17 SO* 18 NC 19 NC 20
40 NC 39 NC 38 NC 37 NC 36 NC 35 I/O7* 34 I/O6* 33 I/O5* 32 I/O4* 31 VCCP* 30 GNDP* 29 I/O3* 28 I/O2* 27 I/O1* 26 I/O0* 25 SER/PAR* 24 NC 23 NC 22 NC 21 NC

Note:
*Optional Use See pin description text for connection information.
7654321
64-megabit 2.7-volt Only Dual-interface

AT45DB642

Note See AT45DCB008 Datasheet.

Block Diagram

However, the use of either interface is purely optional. Its 69,206,016 bits of memory are organized as 8192 pages of 1056 bytes each. In addition to the main memory, the AT45DB642 also contains two SRAM data buffers of 1056 bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed, as well as reading or writing a continuous data stream. EEPROM emulation bit or byte alterability is easily handled with a selfcontained three step Read-Modify-Write operation. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the uses either a serial interface or a parallel interface to sequentially access its data. The simple sequential access facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size and active pin count. DataFlash supports SPI mode 0 and mode The device is optimized for use in many commercial and industrial applications where high-density, low-pin count, low-voltage, and low-power are essential. The device operates at clock frequencies up to 20 MHz with a typical active read current consumption of 4 mA.

To allow for simple in-system reprogrammability, the AT45DB642 does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB642 is enabled through the chip select pin CS and accessed via a three-wire interface consisting of the Serial Input SI , Serial Output SO , and the Serial Clock SCK , or a parallel interface consisting of the parallel input/output pins I/O7 - I/O0 and the clock pin CLK . The SCK and CLK pins are shared and provide the same clocking input to the DataFlash.

All programming cycles are self-timed, and no separate erase cycle is required before programming.

When the device is shipped from Atmel, the most significant page of the memory array may not be erased. In other words, the contents of the last page may not be filled with FFH.

FLASH MEMORY ARRAY

PAGE 1056 BYTES

SCK/CLK CS

RESET VCC GND

RDY/BUSY SER/PAR

BUFFER 1 1056 BYTES

BUFFER 2 1056 BYTES

I/O INTERFACE

SI SO

I/O7 - I/O0

Memory Array

To provide optimal flexibility, the memory array of the AT45DB642 is divided into three levels of granularity comprising of sectors, blocks and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page-by-page basis however, the optional erase operations can be performed at the block or page level.
2 AT45DB642

AT45DB642

Memory Architecture Diagram

SECTOR ARCHITECTURE

SECTOR 0 = 8 Pages 8448 bytes 8K + 256

SECTOR 1 = 248 Pages 261,888 bytes 248K + 7936

SECTOR 2 = 256 Pages 270,336 bytes 256K + 8K

SECTOR 3 = 256 Pages 270,336 bytes 256K + 8K
Ordering Information
fSCK MHz

ICC mA

Active Standby

Note Serial Interface
Ordering Code AT45DB642-TC

AT45DB642-TI

AT45DB642

Package 40T

Operation Range Commercial 0°C to 70°C Industrial
-40°C to 85°C

Package Type
40-lead, Plastic Thin Small Outline Package TSOP

Packaging Information
40T TSOP

PIN 1
0º ~ 8º c

Pin 1 Identifier

SEATING PLANE

GAGE PLANE

This package conforms to JEDEC reference MO-142, Variation CD. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum.

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL A A1 A2 D D1 E L L1 b c e

MIN NOM MAX

BASIC

BASIC

NOTE

Note 2 Note 2
2325 Orchard Parkway R San Jose, CA 95131
40T, 40-lead 10 x 20 mm Package Plastic Thin Small Outline Package, Type I TSOP
10/18/01
36 AT45DB642

Atmel Headquarters

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Atmel Operations

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Datasheet ID: AT45DB642-TC 519052