74F640PC

74F640PC Datasheet

74F640<br>• 74F645 Octal Bus Transceiver with 3-STATE Outputs

Part	Datasheet
74F640PC	74F640PC (pdf)

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74F640 • 74F645 Octal Bus Transceiver with 3-STATE Outputs 74F640 • 74F645 Octal Bus Transceiver with 3-STATE Outputs These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA, have 3STATE outputs, and a common output enable pin. The direction of data flow is determined by the transmit/receive T/R input. The 74F645 is a high speed/low power version of the 74F245. The 74F640 is an inverting option of the 74F645. s Designed for asynchronous two-way data flow between busses s Outputs sink 64 mA s Transmit/receive T/R input controls the direction of data flow s 74F645 is a lower power, faster version of the 74F245 s 74F640 is an inverting option of the 74F645 Ordering Code: Order Number Package Number Package Description 74F640SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F640PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74F645PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram 1999 Fairchild Semiconductor Corporation DS010267 74F640 • 74F645 Unit Loading/Fan Out Pin Names OE T/R Output Enable Input Active LOW Transmit/Receive Input Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 70 µA/−0.4 mA −12 mA/64 mA 70 µA/−0.4 mA −12 mA/64 mA Functional Description The output enable OE is active LOW. If the device is disabled OE HIGH , the outputs are in the high impedance state. The transmit/receive input T/R controls whether data is transmitted from the A bus to the B bus or from the B bus to the A bus. When T/R is LOW, B data is sent to the A bus. If T/R is HIGH, A data is sent to the B bus. Logic Diagram Function Table Inputs Outputs OE T/R 74F640 74F645 L Bus B data to Bus A Bus B data to Bus A L H Bus A data to Bus B Bus A data to Bus B H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance State 74F640 74F645 74F640 • 74F645 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2 −30 mA to mA Voltage Applied to Output in HIGH State with VCC = 0V Standard Output 3-STATE Output −0.5V to VCC −0.5V to +5.5V

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74F640
• 74F645 Octal Bus Transceiver with 3-STATE Outputs
74F640
• 74F645 Octal Bus Transceiver with 3-STATE Outputs

These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA, have 3STATE outputs, and a common output enable pin. The direction of data flow is determined by the transmit/receive T/R input. The 74F645 is a high speed/low power version of the 74F245. The 74F640 is an inverting option of the 74F645.
s Designed for asynchronous two-way data flow between busses
s Outputs sink 64 mA s Transmit/receive T/R input controls the direction of
data flow s 74F645 is a lower power, faster version of the 74F245 s 74F640 is an inverting option of the 74F645
Ordering Code:

Order Number Package Number

Package Description
74F640SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F640PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74F645PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagram
1999 Fairchild Semiconductor Corporation DS010267
74F640
• 74F645

Unit Loading/Fan Out

Pin Names

OE T/R

Output Enable Input Active LOW Transmit/Receive Input Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL
20 µA/−0.6 mA 20 µA/−0.6 mA 70 µA/−0.4 mA −12 mA/64 mA 70 µA/−0.4 mA −12 mA/64 mA

Functional Description

The output enable OE is active LOW. If the device is disabled OE HIGH , the outputs are in the high impedance state. The transmit/receive input T/R controls whether data is transmitted from the A bus to the B bus or from the B bus to the A bus. When T/R is LOW, B data is sent to the A bus. If T/R is HIGH, A data is sent to the B bus.

Logic Diagram

Function Table

Inputs

Outputs

OE T/R
74F640
74F645

L Bus B data to Bus A Bus B data to Bus A

L H Bus A data to Bus B Bus A data to Bus B

H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance State
74F640
74F645
74F640
• 74F645

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Output
in HIGH State with VCC = 0V Standard Output 3-STATE Output
−0.5V to VCC −0.5V to +5.5V

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Datasheet ID: 74F640PC 513361