74F537PC

74F537PC Datasheet

74F537 1-of-10 Decoder with 3-STATE Outputs

Part	Datasheet
74F537PC	74F537PC (pdf)

PDF Datasheet Preview
74F537 1-of-10 Decoder with 3-STATE Outputs 74F537 1-of-10 Decoder with 3-STATE Outputs The 74F537 is one-of-ten decoder/demultiplexer with four active HIGH BCD inputs and ten mutually exclusive outputs. A polarity control input determines whether the outputs are active LOW or active HIGH. The 74F537 has 3STATE outputs, and a HIGH signal on the Output Enable OE input forces all outputs to the high impedance state. Two input enables, active HIGH E2 and active LOW E1, are available for demultiplexing data to the selected output in either non-inverted or inverted form. Input codes greater than BCD nine cause all outputs to go to the inactive state i.e., same polarity as the P input . Ordering Code: Order Number Package Number Package Description 74F537SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F537PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 1999 Fairchild Semiconductor Corporation DS009550 74F537 Unit Loading/Fan Out Pin Names E1 E2 OE P Truth Table Address Inputs Enable Input Active LOW Enable Input Active HIGH Output Enable Input Active LOW Polarity Control Input 3-STATE Outputs U.L. HIGH/LOW 150/40 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA Function High Impedance Disable Active HIGH Output P = L Inputs Outputs OE E1 E2 A3 A2 A1 A0 O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 LXLXXXX Outputs Equal P Input L LHL L LHL L L LHL L LHLHL L L LHL L LHL L L LHL LHHL L LHL L L LHLHL L LHL L LHLHLHL L LHL L LHLHHL L LHL L LHLHHHL L LHL L Active LOW Output P = H L LHHL L LHL L LHHL LHL L LH L LHHXHX L LHHHXX L LHL L LHL L LHL L LHL L LHLHL L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance L LHHL L LHHL L 74F537 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F537 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C

PDF Datasheet Preview

74F537 1-of-10 Decoder with 3-STATE Outputs
74F537 1-of-10 Decoder with 3-STATE Outputs

The 74F537 is one-of-ten decoder/demultiplexer with four active HIGH BCD inputs and ten mutually exclusive outputs. A polarity control input determines whether the outputs are active LOW or active HIGH. The 74F537 has 3STATE outputs, and a HIGH signal on the Output Enable OE input forces all outputs to the high impedance state.

Two input enables, active HIGH E2 and active LOW E1, are available for demultiplexing data to the selected output in either non-inverted or inverted form. Input codes greater than BCD nine cause all outputs to go to the inactive state i.e., same polarity as the P input .
Ordering Code:

Order Number Package Number

Package Description
74F537SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F537PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
1999 Fairchild Semiconductor Corporation DS009550
74F537

Unit Loading/Fan Out

Pin Names

E1 E2 OE P

Truth Table

Address Inputs Enable Input Active LOW Enable Input Active HIGH Output Enable Input Active LOW Polarity Control Input 3-STATE Outputs

U.L. HIGH/LOW
150/40

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA

Function

High Impedance Disable

Active HIGH Output P = L

Inputs

Outputs

OE E1 E2 A3 A2 A1 A0 O0 O1 O2 O3 O4 O5 O6 O7 O8 O9

LXLXXXX

Outputs Equal P Input

L LHL L LHL L

L LHL L LHLHL L

L LHL L LHL L

L LHL LHHL L LHL L

L LHLHL L LHL L LHLHLHL L LHL L LHLHHL L LHL L LHLHHHL L LHL L

Active LOW Output P = H

L LHHL L LHL L LHHL LHL L LH L LHHXHX L LHHHXX L LHL L LHL L LHL L LHL

L LHLHL L

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance

L LHHL L LHHL L
74F537

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F537

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 74F537PC Datasheet file may be downloaded here without warranties.

Datasheet ID: 74F537PC 513343