74F382PC

74F382PC Datasheet

74F382 4-Bit Arithmetic Logic Unit

Part	Datasheet
74F382PC	74F382PC (pdf)

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74F382 4-Bit Arithmetic Logic Unit 74F382 4-Bit Arithmetic Logic Unit The 74F382 performs three arithmetic and three logic operations on two 4-bit words, A and B. Two additional Select input codes force the Function outputs LOW or HIGH. An Overflow output is provided for convenience in twos complement arithmetic. A Carry output is provided for ripple expansion. For high-speed expansion using a Carry Lookahead Generator, refer to the 74F381 data sheet. s Performs six arithmetic and logic functions s Selectable LOW clear and HIGH preset functions s LOW input loading minimizes drive requirements s Carry output for ripple expansion s Overflow output for twos complement arithmetic Ordering Code: Order Number 74F382SC 74F382SJ 74F382PC Package Number Package Description M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Logic Symbols Connection Diagram IEEE/IEC 2004 Fairchild Semiconductor Corporation DS009529 74F382 Unit Loading/Fan Out Pin Names Cn + 4 OVR A Operand Inputs B Operand Inputs Function Select Inputs Carry Input Carry Output Overflow Output Function Outputs U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−2.4 mA 20 µA/−2.4 mA 20 µA/−0.6 mA 20 µA/−3.0 mA −1 mA/20 mA −1 mA/20 mA −1 mA/20 mA Functional Description Signals applied to the Select inputs determine the mode of operation, as indicated in the Function Select Table. An extensive listing of input and output levels is shown in the Truth Table. The circuit performs the arithmetic functions for either active HIGH or active LOW operands, with output levels in the same convention. In the Subtract operating modes, it is necessary to force a carry HIGH for active HIGH operands, LOW for active LOW operands into the Cn input of the least significant package. Ripple expansion is illustrated in Figure The overflow output OVR is the Exclusive-OR of Cn + 3 and Cn + 4 a HIGH signal on OVR indicates overflow in twos complement operation. Typical delays for Figure 2 are given in Figure Function Select Table Select H = HIGH Voltage Level L = LOW Voltage Level Operation S2 L Clear L B Minus A L A Minus B L A Plus B H A+B H AB H Preset Path Segment Toward F A1 or B1 to Cn + 4 Cn to Cn + 4 Cn to Cn + 4 Cn to F Cn to Cn + 4, OVR Total Delay FIGURE 16-Bit Delay Tabulation Output Cn + 4, OVR FIGURE 16-Bit Ripply Carry ALU Expansion 74F382 Truth Table Inputs Outputs Function F3 OVR Cn + 4 CLEAR

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74F382 4-Bit Arithmetic Logic Unit
74F382 4-Bit Arithmetic Logic Unit

The 74F382 performs three arithmetic and three logic operations on two 4-bit words, A and B. Two additional Select input codes force the Function outputs LOW or HIGH. An Overflow output is provided for convenience in twos complement arithmetic. A Carry output is provided for ripple expansion. For high-speed expansion using a Carry Lookahead Generator, refer to the 74F381 data sheet.
s Performs six arithmetic and logic functions s Selectable LOW clear and HIGH preset functions s LOW input loading minimizes drive requirements s Carry output for ripple expansion s Overflow output for twos complement arithmetic
Ordering Code:

Order Number 74F382SC 74F382SJ 74F382PC

Package Number

Package Description

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

Logic Symbols

Connection Diagram

IEEE/IEC
2004 Fairchild Semiconductor Corporation DS009529
74F382

Unit Loading/Fan Out

Pin Names

Cn + 4 OVR

A Operand Inputs B Operand Inputs Function Select Inputs Carry Input Carry Output Overflow Output Function Outputs

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−2.4 mA 20 µA/−2.4 mA 20 µA/−0.6 mA 20 µA/−3.0 mA −1 mA/20 mA −1 mA/20 mA −1 mA/20 mA

Functional Description

Signals applied to the Select inputs determine the mode of operation, as indicated in the Function Select Table. An extensive listing of input and output levels is shown in the Truth Table. The circuit performs the arithmetic functions for either active HIGH or active LOW operands, with output levels in the same convention. In the Subtract operating modes, it is necessary to force a carry HIGH for active HIGH operands, LOW for active LOW operands into the Cn input of the least significant package. Ripple expansion is illustrated in Figure The overflow output OVR is the Exclusive-OR of Cn + 3 and Cn + 4 a HIGH signal on OVR indicates overflow in twos complement operation. Typical delays for Figure 2 are given in Figure

Function Select Table

Select

H = HIGH Voltage Level L = LOW Voltage Level

Operation S2 L Clear L B Minus A L A Minus B L A Plus B H A+B H AB H Preset

Path Segment

Toward F

A1 or B1 to Cn + 4 Cn to Cn + 4 Cn to Cn + 4 Cn to F Cn to Cn + 4, OVR Total Delay

FIGURE 16-Bit Delay Tabulation

Output Cn + 4, OVR

FIGURE 16-Bit Ripply Carry ALU Expansion
74F382

Truth Table

Inputs

Outputs

Function

F3 OVR

Cn + 4

CLEAR

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Datasheet ID: 74F382PC 513331