74F569SC

74F569SC Datasheet

74F569 4-Bit Bidirectional Counter with 3-STATE Outputs

Part	Datasheet
74F569SC	74F569SC (pdf)

Related Parts	Information
74F569PC	74F569PC

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74F569 4-Bit Bidirectional Counter with 3-STATE Outputs 74F569 4-Bit Bidirectional Counter with 3-STATE Outputs Enable OE input forces the output buffers into the high impedance state but does not prevent counting, resetting or parallel loading. s Synchronous counting and loading s Lookahead carry capability for easy cascading s Preset capability for programmable operation s 3-STATE outputs for bus organized systems Ordering Code: Order Number Package Number Package Description 74F569SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F569SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F569PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC is a registered trademark of Fairchild Semiconductor Corporation. 2000 Fairchild Semiconductor Corporation DS009565 74F569 Unit Loading/Fan Out Pin Names CEP CET CP PE U/D OE MR SR TC CC Parallel Data Inputs Count Enable Parallel Input Active LOW Count Enable Trickle Input Active LOW Clock Pulse Input Active Rising Edge Parallel Enable Input Active LOW Up/Down Count Control Input Output Enable Input Active LOW Master Reset Input Active LOW Synchronous Reset Input Active LOW 3-STATE Parallel Data Outputs Terminal Count Output Active LOW Clocked Carry Output Active LOW U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−1.2 mA 20 µA/−0.6 mA 20 µA/−1.2 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA −1 mA/20 mA −1 mA/20 mA Functional Description The 74F569 counts in the modulo-16 binary sequence. From state 15 it will increment to state 0 in the Up mode in the Down mode it will decrement from 0 to The clock inputs of all flip-flops are driven in parallel through a clock buffer. All state changes except due to Master Reset occurs synchronously with the LOW-to-HIGH transition of the Clock Pulse CP input signal. The circuits have five fundamental modes of operation, in order of precedence asynchronous reset, synchronous reset, parallel load, count and hold. Five control Master Reset MR , Synchronous Reset SR , Parallel Enable PE , Count Enable Parallel CEP and Count Enable Trickle the Up/Down U/D input, determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces the flip-flop Q outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows the Q outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data Pn inputs to be loaded into the flip-flops on the next rising edge of CP. With MR, SR and PE HIGH, CEP and CET permit counting when both are LOW. Conversely, a HIGH signal on either CEP or CET inhibits counting. The 74F569 uses edge-triggered flip-flops and changing the SR, PE, CEP, CET or U/D inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count TC output is normally HIGH and goes LOW providing CET is LOW, when the counter reaches zero in the Down mode, or reaches maximum 15 in the Up mode. TC will then remain LOW until a state change occurs, whether by counting or presetting, or until U/D or CET is changed. To implement synchronous multi- stage counters, the connections between the TC output and the CEP and CET inputs can provide either slow or fast carry propagation. Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle takes 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. For such applications, the Clocked Carry CC output is provided. The CC output is normally HIGH. When CEP, CET, and TC are LOW, the CC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again, as shown in the CC Truth Table. When the Output Enable OE is LOW, the parallel data outputs are active and follow the flip-flop Q outputs. A HIGH signal on OE forces to the High Z state but does not prevent counting, loading or resetting. Logic Equations Count Enable = CEP • CET • PE Up TC = Q0 • Q1 • Q2 • Q3 • Up • CET Down TC = Q0 • Q1 • Q2 • Q3 • Down • CET 74F569 CC Truth Table Inputs Output SR PE CEP CET TC CP CC Note 1 LXXX X L XX XXHX XXXH XXXX HHL L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = HIGH-to-LOW-to-HIGH Clock Transition Note 1 TC is generated internally Mode Select Table Inputs Operating

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74F569 4-Bit Bidirectional Counter with 3-STATE Outputs
74F569 4-Bit Bidirectional Counter with 3-STATE Outputs

Enable OE input forces the output buffers into the high impedance state but does not prevent counting, resetting or parallel loading.
s Synchronous counting and loading s Lookahead carry capability for easy cascading s Preset capability for programmable operation s 3-STATE outputs for bus organized systems
Ordering Code:

Order Number Package Number

Package Description
74F569SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F569SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F569PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
is a registered trademark of Fairchild Semiconductor Corporation.
2000 Fairchild Semiconductor Corporation DS009565
74F569

Unit Loading/Fan Out

Pin Names

CEP CET CP PE U/D OE MR SR TC CC

Parallel Data Inputs Count Enable Parallel Input Active LOW Count Enable Trickle Input Active LOW Clock Pulse Input Active Rising Edge Parallel Enable Input Active LOW Up/Down Count Control Input Output Enable Input Active LOW Master Reset Input Active LOW Synchronous Reset Input Active LOW 3-STATE Parallel Data Outputs Terminal Count Output Active LOW Clocked Carry Output Active LOW

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−1.2 mA 20 µA/−0.6 mA 20 µA/−1.2 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA −1 mA/20 mA −1 mA/20 mA

Functional Description

The 74F569 counts in the modulo-16 binary sequence. From state 15 it will increment to state 0 in the Up mode in the Down mode it will decrement from 0 to The clock inputs of all flip-flops are driven in parallel through a clock buffer. All state changes except due to Master Reset occurs synchronously with the LOW-to-HIGH transition of the Clock Pulse CP input signal.

The circuits have five fundamental modes of operation, in order of precedence asynchronous reset, synchronous reset, parallel load, count and hold. Five control Master Reset MR , Synchronous Reset SR , Parallel Enable PE , Count Enable Parallel CEP and Count Enable Trickle the Up/Down U/D input, determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces the flip-flop Q outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows the Q outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data Pn inputs to be loaded into the flip-flops on the next rising edge of CP. With MR, SR and PE HIGH, CEP and CET permit counting when both are LOW. Conversely, a HIGH signal on either CEP or CET inhibits counting.

The 74F569 uses edge-triggered flip-flops and changing the SR, PE, CEP, CET or U/D inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed.

Two types of outputs are provided as overflow/underflow indicators. The Terminal Count TC output is normally HIGH and goes LOW providing CET is LOW, when the counter reaches zero in the Down mode, or reaches maximum
15 in the Up mode. TC will then remain LOW until a state change occurs, whether by counting or presetting, or until U/D or CET is changed. To implement synchronous multi-
stage counters, the connections between the TC output and the CEP and CET inputs can provide either slow or fast carry propagation.

Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle takes 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. For such applications, the Clocked Carry CC output is provided. The CC output is normally HIGH. When CEP, CET, and TC are LOW, the CC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again, as shown in the CC Truth Table. When the Output Enable OE is LOW, the parallel data outputs are active and follow the flip-flop Q outputs. A HIGH signal on OE forces to the High Z state but does not prevent counting, loading or resetting.

Logic Equations

Count Enable = CEP
• CET
• PE

Up TC = Q0
• Q1
• Q2
• Q3
• Up
• CET

Down TC = Q0
• Q1
• Q2
• Q3
• Down
• CET
74F569

CC Truth Table

Inputs

Output

SR PE CEP CET TC CP CC Note 1

LXXX

X L XX

XXHX

XXXH

XXXX HHL L

H = HIGH Voltage Level L = LOW Voltage Level

X = Immaterial = HIGH-to-LOW-to-HIGH Clock Transition

Note 1 TC is generated internally

Mode Select Table

Inputs

Operating

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Datasheet ID: 74F569SC 513353