74F323PC

74F323PC Datasheet

74F323 Octal Universal Shift/Storage Register

Part	Datasheet
74F323PC	74F323PC (pdf)

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74F323 Octal Universal Shift/Storage Register 74F323 Octal Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins The 74F323 is an 8-bit universal shift/storage register with 3-STATE outputs. Its function is similar to the 74F299 with the exception of Synchronous Reset. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin count. Separate serial inputs and outputs are provided for Q0 and Q7 to allow easy cascading. Four operation modes are possible hold store , shift left, shift right and parallel load. s Common parallel I/O for reduced pin count s Additional serial inputs and outputs for expansion s Four operating modes shift left, shift right, load and store s 3-STATE outputs for bus-oriented applications Ordering Code: Order Number Package Number Package Description 74F323SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F323PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 1999 Fairchild Semiconductor Corporation DS009517 74F323 Unit Loading/Fan Out Pin Names CP DS0 DS7 S0, S1 SR OE1, OE2 Q0, Q7 Clock Pulse Input Active Rising Edge Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Synchronous Reset Input Active LOW 3-STATE Output Enable Inputs Active LOW Multiplexed Parallel Data Inputs 3-STATE Parallel Data Outputs Serial Outputs U.L. HIGH/LOW 150/40 Functional Description The 74F323 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1 as shown in the Mode Select Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on SR overrides the Select inputs and allows the flip-flops to be reset by the next rising edge of CP. All other state changes are also initiated by the LOW-to-HIGH CP transition. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, load, hold and reset operations can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation. Logic Diagram Mode Select Table Inputs Response SR L H S1 X H L H S0 X H L Synchronous Reset = LOW Parallel Load I/On Qn Shift Right DS0 Q0, Q0 Q1, etc. Shift Left DS7 Q7, Q7 Q6, etc. H L X Hold H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = LOW-to-HIGH transition Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−1.2 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 70 µA/−0.65 mA −3 mA/24 mA 20 mA −1 mA/20 mA Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F323 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2

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74F323 Octal Universal Shift/Storage Register
74F323 Octal Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins

The 74F323 is an 8-bit universal shift/storage register with 3-STATE outputs. Its function is similar to the 74F299 with the exception of Synchronous Reset. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin count. Separate serial inputs and outputs are provided for Q0 and Q7 to allow easy cascading. Four operation modes are possible hold store , shift left, shift right and parallel load.
s Common parallel I/O for reduced pin count s Additional serial inputs and outputs for expansion s Four operating modes shift left, shift right, load and
store s 3-STATE outputs for bus-oriented applications
Ordering Code:

Order Number Package Number

Package Description
74F323SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F323PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
1999 Fairchild Semiconductor Corporation DS009517
74F323

Unit Loading/Fan Out

Pin Names

CP DS0 DS7 S0, S1 SR OE1, OE2

Q0, Q7

Clock Pulse Input Active Rising Edge Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Synchronous Reset Input Active LOW 3-STATE Output Enable Inputs Active LOW Multiplexed Parallel Data Inputs 3-STATE Parallel Data Outputs Serial Outputs

U.L. HIGH/LOW
150/40

Functional Description

The 74F323 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1 as shown in the Mode Select Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words.

A LOW signal on SR overrides the Select inputs and allows the flip-flops to be reset by the next rising edge of CP. All other state changes are also initiated by the LOW-to-HIGH CP transition. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed.

A HIGH signal on either OE1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, load, hold and reset operations can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation.

Logic Diagram

Mode Select Table

Inputs

Response

SR L H

S1 X H L H

S0 X H L

Synchronous Reset = LOW Parallel Load I/On Qn Shift Right DS0 Q0, Q0 Q1, etc. Shift Left DS7 Q7, Q7 Q6, etc.

H L X Hold

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = LOW-to-HIGH transition

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−1.2 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 70 µA/−0.65 mA −3 mA/24 mA 20 mA −1 mA/20 mA

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F323

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2

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Datasheet ID: 74F323PC 513318