74F193PC

74F193PC Datasheet

74F193 Up/Down Binary Counter with Separate Up/Down Clocks

Part	Datasheet
74F193PC	74F193PC (pdf)

Related Parts	Information
74F193SCX	74F193SCX
74F193SC	74F193SC
74F193SJ	74F193SJ
74F193SJX	74F193SJX

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74F193 Up/Down Binary Counter with Separate Up/Down Clocks 74F193 Up/Down Binary Counter with Separate Up/Down Clocks The 74F193 is an up/down modulo-16 binary counter. Separate Count Up and Count Down Clocks are used, and in either counting mode the circuits operate synchronously. The outputs change state synchronously with the LOW-toHIGH transitions on the clock inputs. Separate Terminal Count Up and Terminal Count Down outputs are provided that are used as the clocks for subsequent stages without extra logic, thus simplifying multi-stage counter designs. Individual preset inputs allow the circuit to be used as a programmable counter. Both the Parallel Load PL and the Master Reset MR inputs asynchronously override the clocks. Ordering Code: Order Number Package Number Package Description 74F193SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74F193SJ Note 1 M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F193PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Note 1 Device not available in Tape and Reel. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009497 74F193 Unit Loading/Fan Out Pin Names CPU CPD MR PL TCD TCU Count Up Clock Input Active Rising Edge Count Down Clock Input Active Rising Edge Asynchronous Master Reset Input Active HIGH Asynchronous Parallel Load Input Active LOW Parallel Data Inputs Flip-Flop Outputs Terminal Count Down Borrow Output Active LOW Terminal Count Up Carry Output Active LOW U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−1.8 mA 20 µA/−1.8 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA −1 mA/20 mA −1 mA/20 mA Functional Description A LOW-to-HIGH transition on the CP input to each flip-flop causes the output to change state. Synchronous switching, as opposed to ripple counting, is achieved by driving the steering gates of all stages from a common Count Up line and a common Count Down line, thereby causing all state changes to be initiated simultaneously. A LOW-to-HIGH transition on the Count Up input will advance the count by one a similar transition on the Count Down input will decrease the count by one. While counting with one clock input, the other should be held HIGH, as indicated in the Function Table. The Terminal Count Up TCU and Terminal Count Down TCD outputs are normally HIGH. When the circuit has reached the maximum count state 15, the next HIGH-toLOW transition of the Count Up Clock will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again, thus effectively repeating the Count Up Clock, but delayed by two gate delays. Similarly, the TCD output will go LOW when the circuit is in the zero state and the Count Down Clock goes LOW. Since the TC outputs repeat the clock waveforms, they can be used as the clock input signals to the next higher order circuit in a multistage counter. TCU = Q0 • Q1 • Q2 • Q3 • CPU TCD = Q0• Q1 • Q2 • Q3 • CPD The 74F193 has an asynchronous parallel load capability permitting the counter to be preset. When the Parallel Load PL and the Master Reset MR inputs are LOW, information present on the Parallel Data input is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs. A HIGH signal on the Master Reset input will disable the preset gates, override both clock inputs, and latch each Q output in the LOW state. If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted. Function Table PL CPU CPD Mode X Reset Asyn. X Preset Asyn. H No Change H Count Up Count Down H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = LOW-to-HIGH Clock Transition State Diagram 74F193 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F193 Absolute Maximum Ratings Note 2 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C

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74F193 Up/Down Binary Counter with Separate Up/Down Clocks
74F193 Up/Down Binary Counter with Separate Up/Down Clocks

The 74F193 is an up/down modulo-16 binary counter. Separate Count Up and Count Down Clocks are used, and in either counting mode the circuits operate synchronously. The outputs change state synchronously with the LOW-toHIGH transitions on the clock inputs. Separate Terminal Count Up and Terminal Count Down outputs are provided
that are used as the clocks for subsequent stages without extra logic, thus simplifying multi-stage counter designs. Individual preset inputs allow the circuit to be used as a programmable counter. Both the Parallel Load PL and the Master Reset MR inputs asynchronously override the clocks.
Ordering Code:

Order Number Package Number

Package Description
74F193SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74F193SJ Note 1

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F193PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Note 1 Device not available in Tape and Reel.

Logic Symbols

Connection Diagram

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009497
74F193

Unit Loading/Fan Out

Pin Names

CPU CPD MR PL TCD TCU

Count Up Clock Input Active Rising Edge Count Down Clock Input Active Rising Edge Asynchronous Master Reset Input Active HIGH Asynchronous Parallel Load Input Active LOW Parallel Data Inputs Flip-Flop Outputs Terminal Count Down Borrow Output Active LOW Terminal Count Up Carry Output Active LOW

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−1.8 mA 20 µA/−1.8 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA −1 mA/20 mA −1 mA/20 mA

Functional Description

A LOW-to-HIGH transition on the CP input to each flip-flop causes the output to change state. Synchronous switching, as opposed to ripple counting, is achieved by driving the steering gates of all stages from a common Count Up line and a common Count Down line, thereby causing all state changes to be initiated simultaneously. A LOW-to-HIGH transition on the Count Up input will advance the count by one a similar transition on the Count Down input will decrease the count by one. While counting with one clock input, the other should be held HIGH, as indicated in the Function Table.

The Terminal Count Up TCU and Terminal Count Down TCD outputs are normally HIGH. When the circuit has reached the maximum count state 15, the next HIGH-toLOW transition of the Count Up Clock will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again, thus effectively repeating the Count Up Clock, but delayed by two gate delays. Similarly, the TCD output will go LOW when the circuit is in the zero state and the Count Down Clock goes LOW. Since the TC outputs repeat the clock waveforms, they can be used as the clock input signals to the next higher order circuit in a multistage counter.

TCU = Q0
• Q1
• Q2
• Q3
• CPU

TCD = Q0• Q1
• Q2
• Q3
• CPD

The 74F193 has an asynchronous parallel load capability permitting the counter to be preset. When the Parallel Load PL and the Master Reset MR inputs are LOW, information present on the Parallel Data input is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs. A HIGH signal on the Master Reset input will disable the preset gates, override both clock inputs, and latch each Q output in the LOW state. If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted.

Function Table

PL CPU CPD

Mode

X Reset Asyn.

X Preset Asyn.

H No Change

H Count Up

Count Down

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = LOW-to-HIGH Clock Transition

State Diagram
74F193

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F193

Absolute Maximum Ratings Note 2

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

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Datasheet ID: 74F193PC 513297