74AC125SCX

74AC125SCX Datasheet

74AC125, 74ACT125 Quad Buffer with 3-STATE Outputs

Part	Datasheet
74AC125SCX	74AC125SCX (pdf)

Related Parts	Information
74AC125SCX_SF500592	74AC125SCX_SF500592
74ACT125SCX	74ACT125SCX
74AC125PC	74AC125PC
74ACT125PC	74ACT125PC
74ACT125SC	74ACT125SC
74AC125SC	74AC125SC
74ACT125MTCX	74ACT125MTCX
74ACT125SJ	74ACT125SJ
74ACT125SJX	74ACT125SJX
74ACT125MTC	74ACT125MTC
74AC125MTCX	74AC125MTCX
74AC125SJ	74AC125SJ
74AC125SJX	74AC125SJX
74AC125MTC	74AC125MTC

PDF Datasheet Preview
74AC125, 74ACT125 Quad Buffer with 3-STATE Outputs January 2008 74AC125, 74ACT125 Quad Buffer with 3-STATE Outputs • ICC reduced by 50% • Outputs source/sink 24mA • ACT125 has TTL-compatible outputs The AC/ACT125 contains four independent non-inverting buffers with 3-STATE outputs. Ordering Information Order Number 74AC125SC 74AC125SJ 74AC125MTC 74AC125PC 74ACT125SC 74ACT125SJ 74ACT125MTC 74ACT125PC Package Number M14A M14D MTC14 N14A M14A M14D MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC J-STD-020B standard. Connection Diagram Logic Symbol IEEE/IEC Pin Description Pin Names An, Bn On Description Inputs Outputs Function Table Inputs Output On L H Z H = HIGH Voltage Level, L = LOW Voltage Level Z = HIGH Impedance, X = Immaterial 74AC125, 74ACT125 Quad Buffer with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter VCC IIK VI IOK VO IO ICC or IGND TSTG TJ Supply Voltage DC Input Diode Current VI = VI = VCC + DC Input Voltage DC Output Diode Current VO = VO = VCC + 0.5V DC Output Voltage DC Output Source or Sink Current DC VCC or Ground Current per Output Pin Storage Temperature Junction Temperature Rating to +7.0V +20mA to VCC + 0.5V +20mA to VCC + 0.5V ±50mA ±50mA to +150°C 140°C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VI VO TA / Parameter Supply Voltage AC ACT Input Voltage Output Voltage Operating Temperature Minimum Input Edge Rate, AC Devices VIN from 30% to 70% of VCC, VCC 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices VIN from 0.8V to 2.0V, VCC 4.5V, 5.5V Rating 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC to +85°C 125mV/ns 125mV/ns 1988 Fairchild Semiconductor Corporation 74AC125, 74ACT125 Quad Buffer with 3-STATE Outputs DC Electrical Characteristics for AC Parameter VIH Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage

PDF Datasheet Preview

74AC125, 74ACT125 Quad Buffer with 3-STATE Outputs

January 2008
74AC125, 74ACT125 Quad Buffer with 3-STATE Outputs
• ICC reduced by 50%
• Outputs source/sink 24mA
• ACT125 has TTL-compatible outputs

The AC/ACT125 contains four independent non-inverting buffers with 3-STATE outputs.
Ordering Information

Order Number 74AC125SC 74AC125SJ 74AC125MTC 74AC125PC 74ACT125SC 74ACT125SJ 74ACT125MTC 74ACT125PC

Package Number

M14A M14D MTC14 N14A M14A M14D MTC14 N14A

Package Description 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC J-STD-020B standard.

Connection Diagram

Logic Symbol

IEEE/IEC

Pin Description

Pin Names An, Bn On

Description Inputs Outputs

Function Table

Inputs

Output On L H Z

H = HIGH Voltage Level, L = LOW Voltage Level Z = HIGH Impedance, X = Immaterial
74AC125, 74ACT125 Quad Buffer with 3-STATE Outputs

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Parameter

VCC IIK

VI IOK

VO IO ICC or IGND TSTG TJ

Supply Voltage DC Input Diode Current

VI = VI = VCC + DC Input Voltage DC Output Diode Current VO = VO = VCC + 0.5V DC Output Voltage DC Output Source or Sink Current DC VCC or Ground Current per Output Pin Storage Temperature Junction Temperature

Rating to +7.0V
+20mA to VCC + 0.5V
+20mA to VCC + 0.5V ±50mA ±50mA to +150°C 140°C

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

Symbol VCC

VI VO TA /

Parameter Supply Voltage

AC ACT Input Voltage Output Voltage Operating Temperature Minimum Input Edge Rate, AC Devices VIN from 30% to 70% of VCC, VCC 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices VIN from 0.8V to 2.0V, VCC 4.5V, 5.5V

Rating
2.0V to 6.0V 4.5V to 5.5V
0V to VCC 0V to VCC to +85°C 125mV/ns
125mV/ns
1988 Fairchild Semiconductor Corporation
74AC125, 74ACT125 Quad Buffer with 3-STATE Outputs

DC Electrical Characteristics for AC

Parameter

VIH Minimum HIGH Level Input Voltage

VIL Maximum LOW Level Input Voltage

VOH Minimum HIGH Level Output Voltage

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Datasheet ID: 74AC125SCX 513076