CY28412OXC

CY28412OXC Datasheet

CY28412

Part	Datasheet
CY28412OXC	CY28412OXC (pdf)

PDF Datasheet Preview
CY28412 Clock Generator for Grantsdale Chipset • Supports P4 and Prescott CPU • Selectable CPU frequencies • Differential CPU clock pairs • 100-MHz differential SRC clocks • 96-MHz differential dot clock • 48-MHz USB clocks • 33-MHz PCI clock • Low-voltage frequency select input • I2C Support with read back capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference EMI reduction • 3.3V power supply • 56-pin SSOP package CPU SRC x2 / x3 x7 / x8 x 8 REF x2 DOT96 USB_48 Block Diagram XIN XOUT CPU_STP# PCI_STP# FS_[C:A] VTT_PWRGD# IREF XTAL OSC PLL Ref Freq PLL1 Divider Network PD PLL2 SDATA SCLK I2C Logic Pin Configuration VDD_REF REF[1:0] PCI0 PCI1 VDD_CPU CPUT[0:1], CPUC[0:1], CPU T/C 2_ITP] VDD_SRC SRCT[0:6], SRCC[0:6], SATA[T/C] VDD_PCI GND_PCI PCI2 PCI3 PCI4 PCI5 GND_PCI VDD_PCI PCI[0:5] VDD_PCI TEST_SEL/PCIF0 VDD_PCIF ITP_EN/PCIF1 PCIF[0:1] VDD_48 USB48/FS_B VDD_48 MHz GND_48 DOT96T Ordering Information Part Number Standard CY28412OC CY28412OCT Lead-free CY28412OXC CY28412OXCT Package Type 56-pin SSOP 56-pin SSOP Tape and Reel 56-pin SSOP 56-pin SSOP Tape and Reel Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C Commercial, 0° to 70°C Commercial, 0° to 70°C Page 15 of 17 [+] Feedback Package Drawing and Dimensions 56-lead Shrunk Small Outline Package O56 CY28412 51-85062-C Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Page 16 of 17 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY28412 Document History Page Document Title CY28412 Clock Generator for Grantsdale Chipset Document Number 38-07612 Description of Change * 131327 12/08/03 RGL New data sheet A 208217 See ECN Corrected Theta JA/JC values Added TCCJ2 specs in the AC Electrical Specs table Added TSKEW2 specs in the AC Electrical Specs table Fixed Figure 7 0.7V Single-ended Load Config Changed max PD supply current from 70 to 75 mA in the AC Electrical Specs table B 249075 See ECN *C 305733 See ECN RGL Changed Single-ended outputs from Rise /Fall times to Edge rate Changed Byte 1 Bit 7 from Reserved to Enable Center Spread Page 17 of 17 [+] Feedback

PDF Datasheet Preview

CY28412

Clock Generator for Grantsdale Chipset
• Supports P4 and Prescott CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100-MHz differential SRC clocks
• 96-MHz differential dot clock
• 48-MHz USB clocks
• 33-MHz PCI clock
• Low-voltage frequency select input
• I2C Support with read back capabilities
• Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference EMI reduction
• 3.3V power supply
• 56-pin SSOP package

CPU SRC
x2 / x3 x7 / x8 x 8

REF x2

DOT96 USB_48

Block Diagram

XIN XOUT

CPU_STP# PCI_STP#

FS_[C:A] VTT_PWRGD#

IREF

XTAL OSC

PLL Ref Freq

PLL1

Divider Network

PD PLL2

SDATA SCLK

I2C Logic

Pin Configuration

VDD_REF REF[1:0]

PCI0 PCI1

VDD_CPU

CPUT[0:1], CPUC[0:1], CPU T/C 2_ITP] VDD_SRC

SRCT[0:6], SRCC[0:6], SATA[T/C]

VDD_PCI GND_PCI

PCI2 PCI3 PCI4 PCI5

GND_PCI

VDD_PCI PCI[0:5]

VDD_PCI TEST_SEL/PCIF0

VDD_PCIF

ITP_EN/PCIF1

PCIF[0:1]

VDD_48

USB48/FS_B

VDD_48 MHz

GND_48 DOT96T
Ordering Information

Part Number Standard CY28412OC CY28412OCT Lead-free CY28412OXC CY28412OXCT

Package Type
56-pin SSOP 56-pin SSOP Tape and Reel
56-pin SSOP 56-pin SSOP Tape and Reel

Product Flow

Commercial, 0° to 70°C Commercial, 0° to 70°C

Commercial, 0° to 70°C Commercial, 0° to 70°C

Page 15 of 17 [+] Feedback

Package Drawing and Dimensions
56-lead Shrunk Small Outline Package O56

CY28412
51-85062-*C

Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

Page 16 of 17

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback

CY28412

Document History Page

Document Title CY28412 Clock Generator for Grantsdale Chipset Document Number 38-07612

Description of Change
** 131327 12/08/03

RGL New data sheet
*A 208217 See ECN

Corrected Theta JA/JC values Added TCCJ2 specs in the AC Electrical Specs table Added TSKEW2 specs in the AC Electrical Specs table Fixed Figure 7 0.7V Single-ended Load Config Changed max PD supply current from 70 to 75 mA in the AC Electrical Specs table
*B 249075 See ECN
*C 305733 See ECN

RGL Changed Single-ended outputs from Rise /Fall times to Edge rate Changed Byte 1 Bit 7 from Reserved to Enable Center Spread

Page 17 of 17
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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY28412OXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY28412OXC 507730