MPC961CFA
MPC961CFA Datasheet
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| Part | Datasheet |
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MPC961CFA |
MPC961CFA (pdf) |
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| MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Order this document by MPC961C/D Low Voltage Zero Delay Buffer The MPC961 is a 2.5V or 3.3V compatible, 1:18 PLL based zero delay buffer. With output frequencies of up to 200MHz, output skews of 150ps the device meets the needs of the most demanding clock tree applications. • Fully Integrated PLL • Up to 200MHz I/O Frequency • LVCMOS Outputs • Outputs Disable in High Impedance • LVCMOS Reference Clock Options • LQFP Packaging • ±50ps Jitter • 150ps Output Skews The MPC961 is offered with two different input configurations. The MPC961C offers an LVCMOS reference clock while the MPC961P offers an LVPECL reference clock. When pulled high the OE pin will force all of the outputs except QFB into a high impedance state. Because the OE pin does not affect the QFB output, down stream clocks can be disabled without the internal PLL losing lock. The MPC961 is fully 2.5V or 3.3V compatible and requires no external loop filter components. All control inputs accept LVCMOS compatible levels and the outputs provide low impedance LVCMOS outputs capable W of driving terminated 50 transmission lines. For series terminated lines the MPC961 can drive two lines per output giving the device an effective fanout of The device is packaged in a 32 lead LQFP. MPC961C LOW VOLTAGE ZERO DELAY BUFFER FA SUFFIX LQFP PACKAGE CASE Freescale Semiconductor, Inc... CCLK Ref PLL 100 200 MHz 50 100 MHz FB_IN F_RANGE 50k QFB The MPC961C requires an external RC filter for the analog power supply pin VCCA. Please see applications section for details. Figure MPC961C Logic Diagram 03/01 Motorola, Inc. 2001 Freescale Semiconductor, Inc... MPC961C Freescale Semiconductor, Inc. 24 23 22 21 20 19 18 17 MPC961C 12345678 FB_IN VCCA F_RANGE CCLK Figure Pinout Top View Table 1 PIN CONFIGURATIONS CCLK Input |
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