MM74HC165SJX

MM74HC165SJX Datasheet

MM74HC165 Parallel-in/Serial-out 8-Bit Shift Register

Part	Datasheet
MM74HC165SJX	MM74HC165SJX (pdf)

Related Parts	Information
MM74HC165MX	MM74HC165MX
MM74HC165MTCX	MM74HC165MTCX
MM74HC165MTC	MM74HC165MTC
MM74HC165M	MM74HC165M
MM74HC165SJ	MM74HC165SJ
MM74HC165N	MM74HC165N

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MM74HC165 Parallel-in/Serial-out 8-Bit Shift Register MM74HC165 Parallel-in/Serial-out 8-Bit Shift Register The MM74HC165 high speed PARALLEL-IN/SERIAL-OUT SHIFT REGISTER utilizes advanced silicon-gate CMOS technology. It has the low power consumption and high noise immunity of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads. This 8-bit serial shift register shifts data from QA to QH when clocked. Parallel inputs to each stage are enabled by a low level at the SHIFT/LOAD input. Also included is a gated CLOCK input and a complementary output from the eighth bit. Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a CLOCK INHIBIT function. Holding either of the CLOCK inputs high inhibits clocking, and holding either CLOCK input low with the SHIFT/LOAD input high enables the other CLOCK input. Data transfer occurs on the positive going edge of the clock. Parallel loading is inhibited as long as the SHIFT/LOAD input is HIGH. When taken LOW, data at the parallel inputs is loaded directly into the register independent of the state of the clock. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. s Typical propagation delay 20 ns clock to Q s Wide operating supply voltage range s Low input current 1 µA maximum s Low quiescent supply current 80 µA maximum 74HC Series s Fanout of 10 LS-TTL loads Ordering Code: Order Number Package Number Package Description MM74HC165M M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow MM74HC165SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide MM74HC165MTC MTC16 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide MM74HC165 N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Pin Assignments for DIP, SOIC, SOP and TSSOP Inputs Internal Output Shift/ Clock Serial Parallel Outputs QH Load Inhibit A. .H QA QB X a. .h a b X QA0 QB0 QH0 H QAN QGN L QAN QGN X QA0 QB0 QH0 H = HIGH Level steady state , L = LOW Level steady state X = Irrelevant any input, including transitions = Transition from LOW-to-HIGH level QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established. QAN, QGN = The level of QA or QG before the most recent transition of the clock indicates a one-bit shift. Top View 1999 Fairchild Semiconductor Corporation DS005316.prf MM74HC165 Logic Diagrams MM74HC165 Absolute Maximum Ratings Note 1 Note 2 Supply Voltage VCC DC Input Voltage VIN DC Output Voltage VOUT Clamp Diode Current IIK, IOK DC Output Current, per pin IOUT DC VCC or GND Current, per pin ICC Storage Temperature Range TSTG Power Dissipation PD Note 3 S.O. Package only Lead Temperature TL Soldering 10 seconds to +7.0V to VCC +1.5V to VCC +0.5V ±20 mA ±25 mA ±50 mA −65°C to +150°C 600 mW 500 mW 260°C Recommended Operating Conditions Min Max Units Supply Voltage VCC DC Input or Output Voltage VIN, VOUT Operating Temperature Range TA −40 +85 Input Rise or Fall Times tr, tf VCC = 2.0V 1000 ns VCC = 4.5V VCC = 6.0V Note 1 Absolute Maximum Ratings are those values beyond which dam-

PDF Datasheet Preview

MM74HC165 Parallel-in/Serial-out 8-Bit Shift Register

MM74HC165 Parallel-in/Serial-out 8-Bit Shift Register

The MM74HC165 high speed PARALLEL-IN/SERIAL-OUT SHIFT REGISTER utilizes advanced silicon-gate CMOS technology. It has the low power consumption and high noise immunity of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads.

This 8-bit serial shift register shifts data from QA to QH when clocked. Parallel inputs to each stage are enabled by a low level at the SHIFT/LOAD input. Also included is a gated CLOCK input and a complementary output from the eighth bit.

Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a CLOCK INHIBIT function. Holding either of the CLOCK inputs high inhibits clocking, and holding either CLOCK input low with the SHIFT/LOAD input high enables the other CLOCK input. Data transfer occurs on the positive going edge of the clock. Parallel
loading is inhibited as long as the SHIFT/LOAD input is HIGH. When taken LOW, data at the parallel inputs is loaded directly into the register independent of the state of the clock.

The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
s Typical propagation delay 20 ns clock to Q s Wide operating supply voltage range s Low input current 1 µA maximum s Low quiescent supply current 80 µA maximum 74HC

Series s Fanout of 10 LS-TTL loads
Ordering Code:

Order Number Package Number

Package Description

MM74HC165M

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

MM74HC165SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide

MM74HC165MTC

MTC16
16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide

MM74HC165

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Pin Assignments for DIP, SOIC, SOP and TSSOP

Inputs

Internal Output

Shift/ Clock Serial Parallel Outputs QH

Load Inhibit

A. .H QA QB

X a. .h a b

X QA0 QB0 QH0

H QAN QGN

L QAN QGN

X QA0 QB0 QH0

H = HIGH Level steady state , L = LOW Level steady state X = Irrelevant any input, including transitions = Transition from LOW-to-HIGH level QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established. QAN, QGN = The level of QA or QG before the most recent transition of the clock indicates a one-bit shift.

Top View
1999 Fairchild Semiconductor Corporation DS005316.prf

MM74HC165

Logic Diagrams

MM74HC165

Absolute Maximum Ratings Note 1

Note 2

Supply Voltage VCC DC Input Voltage VIN DC Output Voltage VOUT Clamp Diode Current IIK, IOK DC Output Current, per pin IOUT DC VCC or GND Current, per pin ICC Storage Temperature Range TSTG Power Dissipation PD

Note 3

S.O. Package only

Lead Temperature TL Soldering 10 seconds
to +7.0V to VCC +1.5V to VCC +0.5V
±20 mA ±25 mA ±50 mA −65°C to +150°C
600 mW 500 mW
260°C

Recommended Operating Conditions

Min Max Units

Supply Voltage VCC DC Input or Output Voltage

VIN, VOUT

Operating Temperature Range TA −40 +85

Input Rise or Fall Times
tr, tf VCC = 2.0V
1000 ns

VCC = 4.5V

VCC = 6.0V

Note 1 Absolute Maximum Ratings are those values beyond which dam-

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Datasheet ID: MM74HC165SJX 634376