MPC9608AC

MPC9608AC Datasheet

MPC9608 Rev 4, 10/2004

Part	Datasheet
MPC9608AC	MPC9608AC (pdf)

Related Parts	Information
MPC9608FA	MPC9608FA

PDF Datasheet Preview
Freescale Semiconductor Technical Data 1:10 LVCMOS Zero Delay Clock Buffer MPC9608 The MPC9608 is a V compatible, 1:10 PLL based zero-delay buffer. With a very wide frequency range and low output skews the MPC9608 is targeted for high performance and mid-range clock tree designs. • 1:10 outputs LVCMOS zero-delay buffer • Single V supply • Supports a clock I/O frequency range of to 200 MHz • Selectable divide-by-two for one output bank • Synchronous output enable control CLK_STOP • Output tristate control output high impedance • PLL bypass mode for low frequency system test purpose • Supports networking, telecommunications and computer applications • Supports a variety of microprocessors and controllers • Compatible to PowerQuicc I and II • Ambient Temperature Range -40°C to +85°C • 32-lead Pb-free Package Available LOW VOLTAGE V LVCMOS 1:10 ZERO-DELAY CLOCK BUFFER FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Functional Description The MPC9608 uses an internal PLL and an external feedback path to lock its AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE low-skew clock output phase to the reference clock phase, providing virtually CASE 873A-03 zero propagation delay. This enables nested clock designs with near-zero insertion delay. Designs using the MPC9608 as PLL fanout buffer will show significantly lower clock skew than clock distributions developed from traditional fanout buffers. The device offers one reference clock input and two banks of 5 outputs for clock fanout. The input frequency and phase is reproduced by the PLL and provided at the outputs. A selectable frequency divider sets the bank B outputs to generate either an identical copy of the bank A clocks or one half of the bank A clock frequency. Both output banks remain synchronized to the input reference for both bank B configurations. Outputs are only disabled or enabled when the outputs are already in logic low state CLK_STOP . For system test and diagnosis, the MPC9608 outputs can also be set to high-impedance state by connecting OE to logic high level. Additionally, the device provides a PLL bypass mode for low frequency test purpose. In PLL bypass mode, the minimum frequency and static phase offset specification do not apply. CLK_STOP and OE do not affect the PLL feedback output QFB and down stream clocks can be disabled without the internal PLL losing lock. The MPC9608 is fully V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines on the incident edge. For series terminated transmission lines, each of the MPC9608 outputs can drive one or two traces giving the devices an effective fanout of The device is packaged in a 7x7 mm2 32-lead LQFP package. Freescale Semiconductor, Inc., All rights reserved. CCLK Bank A QA0 CCLK Ref PLL 00 100-200 MHz STOP 01 50-100 MHz 10 25- 50 MHz FB_IN FB 25 MHz

PDF Datasheet Preview

Freescale Semiconductor Technical Data
1:10 LVCMOS Zero Delay Clock Buffer

MPC9608

The MPC9608 is a V compatible, 1:10 PLL based zero-delay buffer. With a very wide frequency range and low output skews the MPC9608 is targeted for high performance and mid-range clock tree designs.
• 1:10 outputs LVCMOS zero-delay buffer
• Single V supply
• Supports a clock I/O frequency range of to 200 MHz
• Selectable divide-by-two for one output bank
• Synchronous output enable control CLK_STOP
• Output tristate control output high impedance
• PLL bypass mode for low frequency system test purpose
• Supports networking, telecommunications and computer applications
• Supports a variety of microprocessors and controllers
• Compatible to PowerQuicc I and II
• Ambient Temperature Range -40°C to +85°C
• 32-lead Pb-free Package Available

LOW VOLTAGE V LVCMOS 1:10 ZERO-DELAY

CLOCK BUFFER

FA SUFFIX 32-LEAD LQFP PACKAGE

CASE 873A-03

Functional Description The MPC9608 uses an internal PLL and an external feedback path to lock its

AC SUFFIX 32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE
low-skew clock output phase to the reference clock phase, providing virtually

CASE 873A-03
zero propagation delay. This enables nested clock designs with near-zero
insertion delay. Designs using the MPC9608 as PLL fanout buffer will show
significantly lower clock skew than clock distributions developed from traditional
fanout buffers. The device offers one reference clock input and two banks of 5 outputs for clock fanout. The input frequency and
phase is reproduced by the PLL and provided at the outputs. A selectable frequency divider sets the bank B outputs to generate
either an identical copy of the bank A clocks or one half of the bank A clock frequency. Both output banks remain synchronized
to the input reference for both bank B configurations.

Outputs are only disabled or enabled when the outputs are already in logic low state CLK_STOP . For system test and
diagnosis, the MPC9608 outputs can also be set to high-impedance state by connecting OE to logic high level. Additionally, the
device provides a PLL bypass mode for low frequency test purpose. In PLL bypass mode, the minimum frequency and static
phase offset specification do not apply.

CLK_STOP and OE do not affect the PLL feedback output QFB and down stream clocks can be disabled without the internal

PLL losing lock.

The MPC9608 is fully V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS
signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines on
the incident edge. For series terminated transmission lines, each of the MPC9608 outputs can drive one or two traces giving the devices an effective fanout of The device is packaged in a 7x7 mm2 32-lead LQFP package.

Freescale Semiconductor, Inc., All rights reserved.

CCLK

Bank A QA0

CCLK

Ref PLL
00 100-200 MHz

STOP
01 50-100 MHz
10 25- 50 MHz

FB_IN

FB 25 MHz

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MPC9608AC Datasheet file may be downloaded here without warranties.

Datasheet ID: MPC9608AC 635581