MPC9600AE

MPC9600AE Datasheet

Order Number MPC9600/D Rev. 2, 11/2001

Part	Datasheet
MPC9600AE	MPC9600AE (pdf)

Related Parts	Information
MPC9600FA	MPC9600FA

PDF Datasheet Preview
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage V and V CMOS PLL Clock Driver The MPC9600 is a low voltage V or V compatible, 1:21 PLL based clock driver and fanout buffer. With output frequencies up to 200 MHz and output skews of 150 ps, the device meets the needs of the most demanding clock tree applications. MPC9600 Features: • Multiplication of input frequency by 2, 3, 4 and 6 • Distribution of output frequency to 21 outputs organized in three output banks QA0-QA6, QB0-QB6, QC0-QC6, each fully selectable • Fully integrated PLL • Selectable output frequency range is 50 to 100 MHz and 100 to 200 MHz V OR V LOW VOLTAGE CMOS PLL CLOCK DRIVER • Selectable input frequency range is to 33 MHz and 25 to 50 MHz • LVCMOS outputs • Outputs disable to high impedance except QFB • LVCMOS or LVPECL reference clock options • 48 lead QFP packaging • ±50 ps cycle-to-cycle jitter • 150 ps maximum output-to-output skew • 200 ps maximum static phase offset window The MPC9600 is a fully LVCMOS V or V compatible PLL clock driver. The MPC9600 has the capability to generate clock signals of 50 to 200 MHz from clock sources of to 50 MHz. The internal PLL is optimized for this frequency range and does not require external loop filter components. QFB provides an output for the external feedback path to the feedback input FB_IN. The QFB divider ratio is configurable and determines the PLL frequency multiplication factor when QFB is directly connected to FB_IN. The MPC9600 is optimized for minimizing the propagation delay between the clock input and FB_IN. FA SUFFIX LQFP PACKAGE CASE Three output banks of 7 outputs each bank can be individually configured to divide the VCO frequency by 2 or by Combining the feedback and output divider ratios, the MPC9600 is capable to multiply the input frequency by 2, 3, 4 and The reference clock is selectable either LVPECL or LVCMOS. The LVPECL reference clock feature allows the designer to use LVPECL fanout buffers for the inner branches of the clock distribution tree. All control inputs accept LVCMOS compatible levels. The outputs provide low impedance LVCMOS outputs capable of driving parallel terminated 50 transmission to VTT=VCC/2. For series terminated lines the MPC9600 can drive two lines per output giving the device an effective total fanout of With guaranteed maximum output-to-output skew of 150 ps, the MPC9600 PLL clock driver meets the synchronization requirements of the most demanding systems. The VCCA analog power pin doubles as a PLL bypass select line for test purpose. When the VCCA is driven to GND the reference clock will bypass the PLL. The device is packaged in a 48-lead LQFP package to provide optimum combination of board density and performance. Motorola, Inc. 2001 For More Information On This Product, Go to: Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. VCCA VCC 7 CCLK pulldown 0 PCLK pulldn Ref PLL 1 PCLK FB Vcc/2 REF_SEL

PDF Datasheet Preview

Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Low Voltage V and V CMOS PLL Clock Driver

The MPC9600 is a low voltage V or V compatible, 1:21 PLL based clock driver and fanout buffer. With output frequencies up to 200 MHz and output skews of 150 ps, the device meets the needs of the most demanding clock tree applications.

MPC9600

Features:
• Multiplication of input frequency by 2, 3, 4 and 6
• Distribution of output frequency to 21 outputs organized in three output banks QA0-QA6, QB0-QB6, QC0-QC6, each fully selectable
• Fully integrated PLL
• Selectable output frequency range is 50 to 100 MHz and 100 to 200 MHz

V OR V LOW VOLTAGE CMOS PLL CLOCK DRIVER
• Selectable input frequency range is to 33 MHz and 25 to 50 MHz
• LVCMOS outputs
• Outputs disable to high impedance except QFB
• LVCMOS or LVPECL reference clock options
• 48 lead QFP packaging
• ±50 ps cycle-to-cycle jitter
• 150 ps maximum output-to-output skew
• 200 ps maximum static phase offset window

The MPC9600 is a fully LVCMOS V or V compatible PLL clock driver. The MPC9600 has the capability to generate clock signals of 50 to 200 MHz from clock sources of to 50 MHz. The internal PLL is optimized for this frequency range and does not require external loop filter components. QFB provides an output for the external feedback path to the feedback input FB_IN. The QFB divider ratio is configurable and determines the PLL frequency multiplication factor when QFB is directly connected to FB_IN. The MPC9600 is optimized for minimizing the propagation delay between the clock input and FB_IN.

FA SUFFIX LQFP PACKAGE

CASE

Three output banks of 7 outputs each bank can be individually configured to divide the VCO frequency by 2 or by Combining the feedback and output divider ratios, the MPC9600 is capable to multiply the input frequency by 2, 3, 4 and

The reference clock is selectable either LVPECL or LVCMOS. The LVPECL reference clock feature allows the designer to use LVPECL fanout buffers for the inner branches of the clock distribution tree. All control inputs accept LVCMOS compatible levels. The outputs provide low impedance LVCMOS outputs capable of driving parallel terminated 50 transmission to VTT=VCC/2. For series terminated lines the MPC9600 can drive two lines per output giving the device an effective total fanout of With guaranteed maximum output-to-output skew of 150 ps, the MPC9600 PLL clock driver meets the synchronization requirements of the most demanding systems.

The VCCA analog power pin doubles as a PLL bypass select line for test purpose. When the VCCA is driven to GND the reference clock will bypass the PLL.

The device is packaged in a 48-lead LQFP package to provide optimum combination of board density and performance.

Motorola, Inc. 2001

For More Information On This Product, Go to:

Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

VCCA

VCC 7

CCLK
pulldown 0

PCLK
pulldn

Ref PLL 1

PCLK

FB Vcc/2

REF_SEL

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MPC9600AE Datasheet file may be downloaded here without warranties.

Datasheet ID: MPC9600AE 635580