MC88920DW

MC88920DW Datasheet

The MC88920 Clock Driver utilizes loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems. The RST_IN/RST_OUT LOCK pins provide a processor reset function designed specifically for the MC68/EC/LC030/040 microprocessor family.

Part	Datasheet
MC88920DW	MC88920DW (pdf)

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MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Order this document from Logic Marketing Freescale Semiconductor, Inc... Low Skew CMOS PLL Clock Driver With Power-Down/Power-Up Feature The MC88920 Clock Driver utilizes loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems. The RST_IN/RST_OUT LOCK pins provide a processor reset function designed specifically for the MC68/EC/LC030/040 microprocessor family. The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple locations on a board. The PLL also allows the MC88920 to multiply a low frequency input clock and distribute it locally at a higher 2X system frequency. MC88920 LOW SKEW CMOS PLL CLOCK DRIVER With Feature • 2X_Q Output Meets All Requirements of the 20 and 25MHz 68040 Microprocessor PCLK Input Specifications • Three Outputs With Skew <500ps and Six Outputs Total Q3, 2X_Q, With <1ns Skew Each Being Phase and Frequency Locked to the SYNC Input • The Phase Variation From Between SYNC and the ‘Q’ Outputs Is Less Than 600ps Derived From the TPD Specification, Which Defines the Skew • SYNC Input Frequency Range From 5MHZ to 2X_Q FMax/4 DW SUFFIX PLASTIC SOIC PACKAGE CASE • Additional Outputs Available at 2X and ÷2 the System ‘Q’ Frequency. Also a Q 180° Phase Shift Output Available. • All Outputs Have ±36mA Drive Equal High and Low CMOS Levels. Can Drive Either CMOS or TTL Inputs. All Inputs Are Compatible • Test Mode Pin PLL_EN Provided for Low Frequency Testing • Special Mode With 2X_Q, Q0, and Q1 Being Reset With MR , and Other Outputs Remain Running. 2X_Q, Q0 and Q1 Are Guaranteed to Be in Lock 3 Clock Cycles After MR Is Negated Three ‘Q’ outputs are provided with less than 500ps skew between their rising edges. The Q3 output is inverted 180° phase shift from the ‘Q’ outputs. A 2X_Q output runs at twice the ‘Q’ output frequency. The 2X_Q output is ideal for 68040 systems which require a 2X processor clock input, and it meets the tight duty cycle spec of the 20 and 25MHz The Q/2 output runs at 1/2 the ‘Q’ frequency. This output is fed back internally, providing a fixed 2X multiplication from the ‘Q’ outputs to the SYNC input. Since the feedback is done internally no external feedback pin is provided the input/output frequency relationships are fixed. In normal operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88920 in a static ‘test mode’. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency board test environment. The RST_OUT LOCK pin doubles as a indicator. When the RST_IN pin is held high, the open drain RST_OUT pin will be pulled actively low until is achieved. When occurs, the RST_OUT LOCK is released and a resistor will pull the signal high. To give a processor reset signal, the RST_IN pin is toggled low, and the RST_OUT LOCK pin will stay low for 1024 cycles of the ‘Q’ output frequency after the RST_IN pin is brought back high. Description of the RST_IN/RST_OUT LOCK Functionality The RST_IN and RST_OUT LOCK pins provide a 68030/040 processor reset function, with the RST_OUT pin also acting as a lock indicator. If the RST_IN pin is held high during system the RST_OUT pin will be in the low state until steady state phase/frequency lock to the input reference is achieved. 1024 ‘Q’ output cycles after is achieved the RST_OUT LOCK pin will go into a high impedance state, allowing it to be pulled high by an external resistor see the AC/DC specs for the characteristics of the RST_OUT LOCK pin . If the RST_IN pin is held low during the RST_OUT LOCK pin will remain low. 8/95 Motorola, Inc. 1995 Freescale Semiconductor, Inc... MC88920 Freescale Semiconductor, Inc. Mode Functionality The MC88920 has a special feature designed in to allow the processor clock inputs to be reset for total processor and then to return to operation very quickly when the processor is again. The MR pin resets outputs 2X_Q, Q0 and Q1 only leaving the other outputs operational for other system activity. When MR is negated, all outputs will be operating normally within 3 clock cycles. Q3 1 VCC 2 MR 3 RST_IN 4 VCC AN 5 RC1 6 GND AN 7 SYNC 8 GND 9 Q0 10 20 GND 19 2X_Q 18 Q/2 17 VCC 16 Q2 15 GND 14 RST_OUT LOCK 13 PLL_EN 12 Q1 11 VCC Pinout Wide SOIC Package Top View Description of the RST_IN/RST_OUT LOCK Functionality continued After the system is complete and the 88920 is to the SYNC input signal RST_OUT high , the processor reset functionality can be utilized. When the RST_IN pin is toggled low min. pulse width=10nS , RST_OUT LOCK will go to the low state and remain there for 1024 cycles of the ‘Q’ output frequency 512 SYNC cycles . During the time in which the RST_OUT LOCK is actively pulled low, all the 88920 clock outputs will continue operating correctly and in a locked condition to the SYNC input clock signals to the 68030/040 family of processors must continue while the processor is in reset . A propagation delay after the 1024th cycle RST_OUT LOCK goes back to the high impedance state to be pulled high by the resistor.

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MOTOROLA

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Order this document from Logic Marketing

Freescale Semiconductor, Inc...

Low Skew CMOS PLL Clock Driver

With Power-Down/Power-Up Feature

The MC88920 Clock Driver utilizes loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems. The RST_IN/RST_OUT LOCK pins provide a processor reset function designed specifically for the MC68/EC/LC030/040 microprocessor family.

The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple locations on a board. The PLL also allows the MC88920 to multiply a low frequency input clock and distribute it locally at a higher 2X system frequency.

MC88920

LOW SKEW CMOS PLL CLOCK DRIVER

With Feature
• 2X_Q Output Meets All Requirements of the 20 and 25MHz 68040 Microprocessor PCLK Input Specifications
• Three Outputs With Skew <500ps and Six Outputs Total Q3, 2X_Q, With <1ns Skew Each Being Phase and Frequency Locked to the SYNC Input
• The Phase Variation From Between SYNC and the ‘Q’ Outputs Is Less Than 600ps Derived From the TPD Specification, Which Defines the Skew
• SYNC Input Frequency Range From 5MHZ to 2X_Q FMax/4

DW SUFFIX PLASTIC SOIC PACKAGE

CASE
• Additional Outputs Available at 2X and ÷2 the System ‘Q’ Frequency. Also a Q 180° Phase Shift Output Available.
• All Outputs Have ±36mA Drive Equal High and Low CMOS Levels. Can Drive Either CMOS or TTL Inputs. All Inputs Are Compatible
• Test Mode Pin PLL_EN Provided for Low Frequency Testing
• Special Mode With 2X_Q, Q0, and Q1 Being Reset With MR , and Other Outputs Remain Running. 2X_Q, Q0 and Q1 Are Guaranteed to Be in Lock 3 Clock Cycles After MR Is Negated

Three ‘Q’ outputs are provided with less than 500ps skew between their rising edges. The Q3 output is inverted 180° phase shift from the ‘Q’ outputs. A 2X_Q output runs at twice the ‘Q’ output frequency. The 2X_Q output is ideal for 68040 systems which require a 2X processor clock input, and it meets the tight duty cycle spec of the 20 and 25MHz The Q/2 output runs at 1/2 the ‘Q’ frequency. This output is fed back internally, providing a fixed 2X multiplication from the ‘Q’ outputs to the SYNC input. Since the feedback is done internally no external feedback pin is provided the input/output frequency relationships are fixed.

In normal operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88920 in a static ‘test mode’. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency board test environment.

The RST_OUT LOCK pin doubles as a indicator. When the RST_IN pin is held high, the open drain RST_OUT pin will be pulled actively low until is achieved. When occurs, the RST_OUT LOCK is released and a resistor will pull the signal high. To give a processor reset signal, the RST_IN pin is toggled low, and the RST_OUT LOCK pin will stay low for 1024 cycles of the ‘Q’ output frequency after the RST_IN pin is brought back high.

Description of the RST_IN/RST_OUT LOCK Functionality

The RST_IN and RST_OUT LOCK pins provide a 68030/040 processor reset function, with the RST_OUT pin also acting as a lock indicator. If the RST_IN pin is held high during system the RST_OUT pin will be in the low state until steady state phase/frequency lock to the input reference is achieved. 1024 ‘Q’ output cycles after is achieved the RST_OUT LOCK pin will go into a high impedance state, allowing it to be pulled high by an external resistor see the AC/DC specs for the characteristics of the RST_OUT LOCK pin . If the RST_IN pin is held low during the RST_OUT LOCK pin will remain low.
8/95

Motorola, Inc. 1995

Freescale Semiconductor, Inc...

MC88920

Freescale Semiconductor, Inc.

Mode Functionality The MC88920 has a special feature
designed in to allow the processor clock inputs to be reset for total processor and then to return to operation very quickly when the processor is again.

The MR pin resets outputs 2X_Q, Q0 and Q1 only leaving the other outputs operational for other system activity. When MR is negated, all outputs will be operating normally within 3 clock cycles.

Q3 1 VCC 2 MR 3 RST_IN 4 VCC AN 5 RC1 6 GND AN 7 SYNC 8 GND 9

Q0 10
20 GND 19 2X_Q 18 Q/2 17 VCC 16 Q2 15 GND 14 RST_OUT LOCK 13 PLL_EN 12 Q1 11 VCC

Pinout Wide SOIC Package Top View

Description of the RST_IN/RST_OUT LOCK Functionality continued

After the system is complete and the 88920 is to the SYNC input signal RST_OUT high , the processor reset functionality can be utilized. When the RST_IN pin is toggled low min. pulse width=10nS , RST_OUT LOCK will go to the low state and remain there for 1024 cycles of the ‘Q’ output frequency 512 SYNC cycles . During the time in which the RST_OUT LOCK is actively pulled low, all the 88920 clock outputs will continue operating correctly and in a locked condition to the SYNC input clock signals to the 68030/040 family of processors must continue while the processor is in reset . A propagation delay after the 1024th cycle RST_OUT LOCK goes back to the high impedance state to be pulled high by the resistor.

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Datasheet ID: MC88920DW 635501