MC100ES6111FAR2

MC100ES6111FAR2 Datasheet

MC100ES6111 Rev. 5, 07/2005

Part	Datasheet
MC100ES6111FAR2	MC100ES6111FAR2 (pdf)

Related Parts	Information
MC100ES6111AC	MC100ES6111AC
MC100ES6111FA	MC100ES6111FA

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Freescale Semiconductor Technical Data Low Voltage V Differential ECL/PECL/HSTL Fanout Buffer MC100ES6111 The MC100ES6111 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6111 supports various applications that require distribution of precisely aligned differential clock signals. Using SiGe:C technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems. LOW-VOLTAGE 1:10 DIFFERENTIAL ECL/PECL/HSTL CLOCK FANOUT DRIVER • 1:10 differential clock distribution • 35 ps maximum device skew • Fully differential architecture from input to all outputs • SiGe:C technology supports near-zero output skew • Supports DC to GHz operation of clock or data signals • ECL/PECL compatible differential clock outputs • ECL/PECL/HSTL compatible differential clock inputs • Single V, V, V or V supply • Standard 32-lead LQFP package • 32-lead Pb-free package available • Industrial temperature range • Pin and function compatible to the MC100EP111 FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-04 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-04 Functional Description The MC100ES6111 is designed for low skew clock distribution systems and supports clock frequencies up to GHz. The device accepts two clock sources. The CLKA input can be driven by ECL or PECL compatible signals, the CLKB input accepts HSTL compatible signals. The selected input signal is distributed to 10 identical, differential ECL/PECL outputs. If VBB is connected to the CLKA input and bypassed to GND by a 10 nF capacitor, the MC100ES6111 can be driven by single-ended ECL/ PECL signals utilizing the VBB bias voltage output. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The MC100ES6111 can be operated from a single V or V supply. As most other ECL compatible devices, the MC100ES6111 supports positive PECL and negative ECL supplies. The MC100ES6111 is pin and function compatible to the MC100EP111. Freescale Semiconductor, Inc., All rights reserved. CLKA CLKB CLK_SEL 24 23 22 21 20 19 18 17 Q1 Q2 Q2 Q3 Q3 Q4 MC100ES6111 Q5 Q6 Q6 Q7 12345678 CLKB CLKB CLKA CLKA CLK_SEL Figure MC100ES6111 Logic Diagram Figure 32-Lead Package Pinout Top View Table Pin Configuration Type Function CLKA, CLKA Input ECL/PECL Differential reference clock signal input

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Freescale Semiconductor Technical Data

Low Voltage V Differential ECL/PECL/HSTL Fanout Buffer

MC100ES6111

The MC100ES6111 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6111 supports various applications that require distribution of precisely aligned differential clock signals. Using SiGe:C technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems.

LOW-VOLTAGE 1:10 DIFFERENTIAL ECL/PECL/HSTL

CLOCK FANOUT DRIVER
• 1:10 differential clock distribution
• 35 ps maximum device skew
• Fully differential architecture from input to all outputs
• SiGe:C technology supports near-zero output skew
• Supports DC to GHz operation of clock or data signals
• ECL/PECL compatible differential clock outputs
• ECL/PECL/HSTL compatible differential clock inputs
• Single V, V, V or V supply
• Standard 32-lead LQFP package
• 32-lead Pb-free package available
• Industrial temperature range
• Pin and function compatible to the MC100EP111

FA SUFFIX 32-LEAD LQFP PACKAGE

CASE 873A-04

AC SUFFIX 32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE CASE 873A-04

Functional Description

The MC100ES6111 is designed for low skew clock distribution systems and supports clock frequencies up to GHz. The device accepts two clock sources. The CLKA input can be driven by ECL or PECL compatible signals, the CLKB input accepts HSTL compatible signals. The selected input signal is distributed to 10 identical, differential ECL/PECL outputs. If VBB is connected to the CLKA input and bypassed to GND by a 10 nF capacitor, the MC100ES6111 can be driven by single-ended ECL/ PECL signals utilizing the VBB bias voltage output.

In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated.

The MC100ES6111 can be operated from a single V or V supply. As most other ECL compatible devices, the MC100ES6111 supports positive PECL and negative ECL supplies. The MC100ES6111 is pin and function compatible to the MC100EP111.

Freescale Semiconductor, Inc., All rights reserved.

CLKA

CLKB

CLK_SEL
24 23 22 21 20 19 18 17

Q1 Q2

Q2 Q3

Q3 Q4

MC100ES6111

Q5 Q6

Q6 Q7
12345678

CLKB

CLKB

CLKA

CLKA

CLK_SEL

Figure MC100ES6111 Logic Diagram

Figure 32-Lead Package Pinout Top View

Table Pin Configuration

Type

Function

CLKA, CLKA

Input

ECL/PECL

Differential reference clock signal input

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Datasheet ID: MC100ES6111FAR2 635460