MT9VDDF6472G-40BD3

MT9VDDF6472G-40BD3 Datasheet

MT9VDDF3272 256MB MT9VDDF6472 512MB

Part	Datasheet
MT9VDDF6472G-40BD3	MT9VDDF6472G-40BD3 (pdf)

Related Parts	Information
MT9VDDF3272G-40BG3	MT9VDDF3272G-40BG3
MT9VDDF6472G-40BF1	MT9VDDF6472G-40BF1

PDF Datasheet Preview
256MB, 512MB x72, ECC, SR PC3200 184-PIN DDR SDRAM RDIMM DDR SDRAM REGISTERED DIMM MT9VDDF3272 256MB MT9VDDF6472 512MB For the latest data sheet, please refer to the Web site: • 184-pin, dual in-line memory module DIMM • Fast data transfer rates PC3200 • Utilizes 400 MT/s DDR SDRAM components • Registered Inputs with one-clock delay • Phase-lock loop PLL clock driver to reduce loading • Supports ECC error detection and correction • 256MB 32 Meg x 72 and 512MB 64 Meg x 72 • VDD = VDDQ = +2.6V • VDDSPD = +2.3V to +3.6V • 2.5V I/O SSTL_2 compatible • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • Internal, pipelined double data rate DDR architecture two data accesses per clock cycle • Bidirectional data strobe DQS transmitted/ received with source-synchronous data capture • Differential clock inputs CK and CK# • Four internal device banks for concurrent operation • Programmable burst lengths 2, 4, or 8 • Auto precharge option • Auto Refresh and Self Refresh Modes • 7.8125µs maximum average periodic refresh interval • Serial Presence-Detect SPD with EEPROM • Programmable READ CAS latency • Gold edge contacts Figure 1 184-Pin DIMM MO-206 Low-Profile 1.125in. 28.58mm Very Low-Profile 0.72in. 18.29mm OPTIONS • Package 184-pin DIMM standard 184-pin DIMM lead-free • Memory Clock, Speed, CAS Latency2 5ns 200 MHz , 400 MT/s, CL = 3 • PCB Low-Profile 1.125in. 28.58mm Very Low-Profile 0.72in. 18.29mm MARKING -40B NOTE Consult Micron for product availability. CL = CAS READ Latency registered mode will add one clock cycle to CL. Table 1 Address Table Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing 256MB 8K 4 BA0, BA1 256Mb 32 Meg x 8 1K 1 S0# 512MB 8K 4 BA0, BA1 512Mb 64 Meg x 8 2K A11 1 S0# 2004 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 256MB, 512MB x72, ECC, SR PC3200 184-PIN DDR SDRAM RDIMM Table 2 Part Numbers and Timing Parameters MODULE DENSITY CONFIGURATION MODULE MEMORY CLOCK/ LATENCY BANDWIDTH DATA RATE CL - tRCD - tRP MT9VDDF3272G-40B__ MT9VDDF3272Y-40B__ MT9VDDF6472G-40B__ MT9VDDF6472Y-40B__ 256MB 512MB 32 Meg x 72 32 Meg x 72 64 Meg x 72 64 Meg x 72 GB/s GB/s GB/s GB/s The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page Figure 5 Mode Register Definition Diagram BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register . M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 Burst Length M3 = 0 Reserved 2 4 8 Reserved M3 = 1 Reserved 2 4 8 Reserved Burst Type Sequential Interleaved M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved 2 3 Reserved M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - -- M6-M0 Valid Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. 256MB, 512MB x72, ECC, SR PC3200 184-PIN DDR SDRAM RDIMM Table 6 Burst Definition Table BURST LENGTH STARTING COLUMN ADDRESS ORDER OF ACCESSES WITHIN A BURST TYPE = TYPE = SEQUENTIAL INTERLEAVED A1 A0 0-1-2-3 0-1-2-3 1-2-3-0 1-0-3-2 2-3-0-1 2-3-0-1 3-0-1-2 3-2-1-0 A2 A1 A0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

PDF Datasheet Preview

256MB, 512MB x72, ECC, SR PC3200 184-PIN DDR SDRAM RDIMM

DDR SDRAM REGISTERED DIMM

MT9VDDF3272 256MB MT9VDDF6472 512MB

For the latest data sheet, please refer to the Web site:
• 184-pin, dual in-line memory module DIMM
• Fast data transfer rates PC3200
• Utilizes 400 MT/s DDR SDRAM components
• Registered Inputs with one-clock delay
• Phase-lock loop PLL clock driver to reduce loading
• Supports ECC error detection and correction
• 256MB 32 Meg x 72 and 512MB 64 Meg x 72
• VDD = VDDQ = +2.6V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O SSTL_2 compatible
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs center-
aligned with data for WRITEs
• Internal, pipelined double data rate DDR
architecture two data accesses per clock cycle
• Bidirectional data strobe DQS transmitted/
received with source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 7.8125µs maximum average periodic refresh interval
• Serial Presence-Detect SPD with EEPROM
• Programmable READ CAS latency
• Gold edge contacts

Figure 1 184-Pin DIMM MO-206

Low-Profile 1.125in. 28.58mm

Very Low-Profile 0.72in. 18.29mm

OPTIONS
• Package 184-pin DIMM standard 184-pin DIMM lead-free
• Memory Clock, Speed, CAS Latency2 5ns 200 MHz , 400 MT/s, CL = 3
• PCB Low-Profile 1.125in. 28.58mm Very Low-Profile 0.72in. 18.29mm

MARKING
-40B

NOTE Consult Micron for product availability.

CL = CAS READ Latency registered mode will add one clock cycle to CL.

Table 1 Address Table

Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing
256MB
8K 4 BA0, BA1 256Mb 32 Meg x 8 1K
1 S0#
512MB
8K 4 BA0, BA1 512Mb 64 Meg x 8 2K A11
1 S0#
2004 Micron Technology, Inc. All rights reserved.

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
256MB, 512MB x72, ECC, SR PC3200 184-PIN DDR SDRAM RDIMM

Table 2 Part Numbers and Timing Parameters

MODULE DENSITY

CONFIGURATION MODULE MEMORY CLOCK/

LATENCY

BANDWIDTH

DATA RATE

CL - tRCD - tRP

MT9VDDF3272G-40B__ MT9VDDF3272Y-40B__ MT9VDDF6472G-40B__ MT9VDDF6472Y-40B__
256MB 512MB
32 Meg x 72 32 Meg x 72 64 Meg x 72 64 Meg x 72

GB/s GB/s GB/s GB/s
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page

Figure 5 Mode Register Definition Diagram

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register .

M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11

Burst Length

M3 = 0 Reserved
2 4 8 Reserved

M3 = 1 Reserved
2 4 8 Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4 000 001 010 011 100 101 110 111

CAS Latency Reserved 2 3 Reserved

M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - --

M6-M0 Valid

Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.
256MB, 512MB x72, ECC, SR PC3200 184-PIN DDR SDRAM RDIMM

Table 6 Burst Definition Table

BURST LENGTH

STARTING COLUMN ADDRESS

ORDER OF ACCESSES WITHIN A BURST

TYPE =

TYPE =

SEQUENTIAL INTERLEAVED

A1 A0
0-1-2-3
0-1-2-3
1-2-3-0
1-0-3-2
2-3-0-1
2-3-0-1
3-0-1-2
3-2-1-0

A2 A1 A0
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MT9VDDF6472G-40BD3 Datasheet file may be downloaded here without warranties.

Datasheet ID: MT9VDDF6472G-40BD3 648504