MT48H16M32LFCM-75 IT:A TR
MT48H16M32LFCM-75 IT:A TR Datasheet
MT48H32M16LF 8 Meg x 16 x 4 banks MT48H16M32LF/LG 4 Meg x 32 x 4 banks
| Part | Datasheet |
|---|---|
MT48H16M32LFCM-75 IT:A TR |
MT48H16M32LFCM-75 IT:A TR (pdf) |
| Related Parts | Information |
|---|---|
MT48H16M32LFCM-75:A TR |
MT48H16M32LFCM-75:A TR |
MT48H32M16LFCJ-75 L IT:A TR |
MT48H32M16LFCJ-75 L IT:A TR |
MT48H32M16LFCJ-75:A TR |
MT48H32M16LFCJ-75:A TR |
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| 512Mb 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Features Mobile SDRAM MT48H32M16LF 8 Meg x 16 x 4 banks MT48H16M32LF/LG 4 Meg x 32 x 4 banks • Fully synchronous all signals registered on positive edge of system clock • VDD = VDDQ = • Internal, pipelined operation column address can be changed every clock cycle • Four internal banks for concurrent operation • Programmable burst lengths 1, 2, 4, 8, and continuous1 • Auto precharge, includes concurrent auto precharge • Auto refresh and self refresh modes • LVTTL-compatible inputs and outputs • On-chip temperature sensor to control refresh rate • Partial-array self refresh PASR • Deep power-down DPD • Selectable output drive DS Table 1 Configuration Addressing DQ Bus Width Architecture Number of banks Bank address balls Row address balls Column address balls Row address balls Column address balls JEDECStandard Option 4 BA0, BA1 Reduced Page-Size Option2 4 BA0, BA1 Table 2: Speed Grade -75 -8 Key Timing Parameters CL = CAS READ latency Clock Rate MHz CL = 2 104 100 CL = 3 133 125 Access Time CL = 2 9ns CL = 3 6ns 7ns Options Marking • VDD/VDDQ 1.8V/1.8V • Row size option Standard addressing option Reduced page-size option LF LG3, 4 • Configuration 32 Meg x 16 8 Meg x 16 x 4 banks 32M16 16 Meg x 32 4 Meg x 32 x 4 banks 16M32 The ordering of accesses within a burst is determined by the BL, the burst type, and the starting column address, as shown in Table 4 on page Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved. 512Mb 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Register Definition Figure 6: Mode Register Definition BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus M14 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved1 WB Op Mode CAS Latency BT Burst Length Mode Register Mx M14 M13 Mode Register Definition 0 Base mode register 0 1 Reserved 1 0 Extended mode register 1 Reserved Write Burst Mode 0 Programmed burst length 1 Single location access M8 M7 Operating Mode 0 Normal operation All other states reserved M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved 2 3 Reserved M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 Burst Length M3 = 0 M3 = 1 Reserved Reserved Reserved Reserved Burst Type Sequential Interleaved Notes Should be programmed to “0” to ensure compatibility with future devices. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved. 512Mb 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Register Definition Table 4 Burst Definition Table Burst Length Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-0 0-1-2-3 1-0-3-2-3-0-1 3-2-1-0 |
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