MT40A1G8SA-075:H

MT40A1G8SA-075:H Datasheet

MT40A2G4 MT40A1G8 MT40A512M16

Part	Datasheet
MT40A1G8SA-075:H	MT40A1G8SA-075:H (pdf)

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8Gb x4, x8, x16 DDR4 SDRAM Features DDR4 SDRAM MT40A2G4 MT40A1G8 MT40A512M16 • VDD = VDDQ = 1.2V ±60mV • VPP = 2.5V, +250mV • On-die, internal, adjustable VREFDQ generation • 1.2V pseudo open-drain I/O • TC maximum up to 95°C 64ms, 8192-cycle refresh up to 85°C 32ms, 8192-cycle refresh at >85°C to 95°C • 16 internal banks x4, x8 4 groups of 4 banks each • 8 internal banks x16 2 groups of 4 banks each • 8n-bit prefetch architecture • Programmable data strobe preambles • Data strobe preamble training • Command/Address latency CAL • Multipurpose register READ and WRITE capability • Write and read leveling • Self refresh mode • Low-power auto self refresh LPASR • Temperature controlled refresh TCR • Fine granularity refresh • Self refresh abort • Maximum power saving • Output driver calibration • Nominal, park, and dynamic on-die termination ODT • Data bus inversion DBI for data bus • Command/Address CA parity • Databus write cyclic redundancy check CRC • Per-DRAM addressability • Connectivity test x16 • JEDEC JESD-79-4 compliant • sPPR and hPPR capability Options1 • Configuration 2 Gig x 4 1 Gig x 8 512 Meg x 16 • Timing cycle time 0.625ns CL = 22 DDR4-3200 0.682ns CL = 21 DDR4-2933 0.750ns CL = 19 DDR4-2666 0.750ns CL = 18 DDR4-2666 0.833ns CL = 17 DDR4-2400 0.833ns CL = 16 DDR4-2400 0.937ns CL = 15 DDR4-2133 1.071ns CL = 13 DDR4-1866 • Operating temperature Commercial 0° TC 95°C Industrial TC 95°C Marking 2G4 1G8 512M16 PM WE SA HA JY LY -062E -068 -075 -075E -083 -083E -093E -107E None IT :A, :B, :D, :G, :E, :H Note: Not all options listed can be combined to define an offered product. Use the part catalog search on for available offerings. Table 1 Key Timing Parameters Speed Grade -062E6 -0685 -0754 -075E4 Data Rate MT/s 3200 2933 2666 Target CL-tRCD-tRP 22-22-22 21-21-21 19-19-19 18-18-18 CL ns tRCD ns tRP ns Micron Technology, Inc. reserves the right to change products or specifications without notice. 2015 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 8Gb x4, x8, x16 DDR4 SDRAM Features Table 1 Key Timing Parameters Continued Speed Grade -0833 -083E3 -093E2 -107E1 Data Rate MT/s 2400 2133 1866 Target CL-tRCD-tRP 17-17-17 16-16-16 15-15-15 13-13-13 CL ns tRCD ns tRP ns Backward compatible to 1600, CL = Backward compatible to 1600, CL = 11 and 1866, CL = Backward compatible to 1600, CL = 11 1866, CL = 13 and 2133, CL = Backward compatible to 1600, CL = 11 1866, CL = 13 2133, CL = 15 and 2400, CL = Backward compatible to 1600, CL = 11 1866, CL = 13 2133, CL = 15 2400, CL = 17 and 2666, CL = Speed offering may have restricted availability. Backward compatible to 1600, CL = 11 1866, CL = 13 2133, CL = 15 2400, CL = 17 2666, CL = Speed offering may have restricted availability. Table 2 Addressing Parameter Number of bank groups Bank group address Bank count per group Bank address in bank group Row addressing Column addressing Page size1 2048 Meg x 4 VREFDQ Range and Levels 120 VREFDQ Step Size 120 VREFDQ Increment and Decrement Timing 121 VREFDQ Target Settings 125 Connectivity Test Mode 127 Pin Mapping 127 Minimum Terms Definition for Logic Equations 128 Logic Equations for a x4 Device 128 Logic Equations for a x8 Device 129 Logic Equations for a x16 Device 129 CT Input Timing Requirements 129 Excessive Row Activation 131 Post Package Repair 132 Post Package Repair 132 Hard Post Package Repair 133 hPPR Row Repair - Entry 133 hPPR Row Repair WRA Initiated REF Commands Allowed 133 hPPR Row Repair WR Initiated REF Commands NOT Allowed 135 sPPR Row Repair 137 hPPR/sPPR Support Identifier 140 ACTIVATE Command 140 PRECHARGE Command 141 REFRESH Command 142 Temperature-Controlled Refresh Mode 144 TCR Mode Normal Temperature Range 144 TCR Mode Extended Temperature Range 144 Fine Granularity Refresh Mode 146 Mode Register and Command Truth Table 146 tREFI and tRFC Parameters 146 Changing Refresh Rate 149 Usage with TCR Mode 149 Self Refresh Entry and Exit 149 SELF REFRESH Operation 151 Self Refresh Abort 153 Self Refresh Exit with NOP Command 154 Power-Down Mode 156 Power-Down Clarifications Case 1 161 Power-Down Entry, Exit Timing with CAL 162 ODT Input Buffer Disable Mode for Power-Down 164 CRC Write Data Feature 166 CRC Write Data 166 WRITE CRC DATA Operation 166 DBI_n and CRC Both Enabled 167 DM_n and CRC Both Enabled 167 DM_n and DBI_n Conflict During Writes with CRC Enabled 167 CRC and Write Preamble Restrictions 167 CRC Simultaneous Operation Restrictions 167 CRC Polynomial 167 CRC Combinatorial Logic Equations 168 Burst Ordering for BL8 169 CRC Data Bit Mapping 169 CRC Enabled With BC4 170 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2015 Micron Technology, Inc. All rights reserved. 8Gb x4, x8, x16 DDR4 SDRAM Features CRC with BC4 Data Bit Mapping 170 CRC Equations for x8 Device in BC4 Mode with A2 = 0 and A2 = 1 173 CRC Error Handling 175 CRC Write Data Flow Diagram 176 Data Bus Inversion 177 DBI During a WRITE Operation 177 DBI During a READ Operation 178 Data Mask 179 Programmable Preamble Modes and DQS Postambles 181 WRITE Preamble Mode 181 READ Preamble Mode 184 READ Preamble Training 184 WRITE Postamble 185 READ Postamble 185 Bank Access Operation 187 READ Operation 191 Read Timing Definitions 191 Read Timing Clock-to-Data Strobe Relationship 192 Read Timing Data Strobe-to-Data Relationship 194 tLZ DQS , tLZ DQ , tHZ DQS , and tHZ DQ Calculations 195 tRPRE Calculation 196 tRPST Calculation 197 READ Burst Operation 198 READ Operation Followed by Another READ Operation 200 READ Operation Followed by WRITE Operation 205 READ Operation Followed by PRECHARGE Operation 211 READ Operation with Read Data Bus Inversion DBI 214 READ Operation with Command/Address Parity CA Parity 215 READ Followed by WRITE with CRC Enabled 217 READ Operation with Command/Address Latency CAL Enabled 218 WRITE Operation 220 Write Timing Definitions 220 Write Timing Clock-to-Data Strobe Relationship 220 tWPRE Calculation 222 tWPST Calculation 223 Write Timing Data Strobe-to-Data Relationship 223 WRITE Burst Operation 227 WRITE Operation Followed by Another WRITE Operation 229 WRITE Operation Followed by READ Operation 235 WRITE Operation Followed by PRECHARGE Operation 239 WRITE Operation with WRITE DBI Enabled 242 WRITE Operation with CA Parity Enabled 244 WRITE Operation with Write CRC Enabled 245 Write Timing Violations 250 Motivation 250 Data Setup and Hold Violations 250 Strobe-to-Strobe and Strobe-to-Clock Violations 250 ZQ CALIBRATION Commands 251 On-Die Termination 253 ODT Mode Register and ODT State Table 253 ODT Read Disable State Table 254 Synchronous ODT Mode 255 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2015 Micron Technology, Inc. All rights reserved. 8Gb x4, x8, x16 DDR4 SDRAM Features ODT Latency and Posted ODT 255 Timing Parameters 255 ODT During Reads 257 Dynamic ODT 258 Functional Description 258 Asynchronous ODT Mode 261 Electrical Specifications 262 Absolute Ratings 262 DRAM Component Operating Temperature Range 262 Electrical Characteristics AC and DC Operating Conditions 263 Supply Operating Conditions 263 Leakages 264 VREFCA Supply 264 VREFDQ Supply and Calibration Ranges 265 VREFDQ Ranges 266 Electrical Characteristics AC and DC Single-Ended Input Measurement Levels 267 RESET_n Input Levels 267 Command/Address Input Levels 267 Command, Control, and Address Setup, Hold, and Derating 269 Data Receiver Input Requirements 271 Connectivity Test CT Mode Input Levels 275 Electrical Characteristics AC and DC Differential Input Measurement Levels 279 Differential Inputs 279 Single-Ended Requirements for CK Differential Signals 280 Slew Rate Definitions for CK Differential Input Signals 281 CK Differential Input Cross Point Voltage 282 DQS Differential Input Signal Definition and Swing Requirements 284 DQS Differential Input Cross Point Voltage 286 Slew Rate Definitions for DQS Differential Input Signals 287 Electrical Characteristics Overshoot and Undershoot Specifications 289 Address, Command, and Control Overshoot and Undershoot Specifications 289 Clock Overshoot and Undershoot Specifications 289 Data, Strobe, and Mask Overshoot and Undershoot Specifications 290 Electrical Characteristics AC and DC Output Measurement Levels 291 Single-Ended Outputs 291 Differential Outputs 292 Reference Load for AC Timing and Output Slew Rate 294 Connectivity Test Mode Output Levels 294 Electrical Characteristics AC and DC Output Driver Characteristics 296 Connectivity Test Mode Output Driver Electrical Characteristics 296 Output Driver Electrical Characteristics 297 Output Driver Temperature and Voltage Sensitivity 300 Alert Driver 300 Electrical Characteristics On-Die Termination Characteristics 302 ODT Levels and I-V Characteristics 302 ODT Temperature and Voltage Sensitivity 303 ODT Timing Definitions 304 DRAM Package Electrical Specifications 307 Thermal Characteristics 311 Current Specifications Measurement Conditions 312 IDD, IPP, and IDDQ Measurement Conditions 312 IDD Definitions 314 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2015 Micron Technology, Inc. All rights reserved. 8Gb x4, x8, x16 DDR4 SDRAM Features Current Specifications Patterns and Test Conditions 318 Current Test Definitions and Patterns 318 IDD Specifications 327 Current Specifications Limits 328 Speed Bin Tables 342 Refresh Parameters By Device Density 351 Electrical Characteristics and AC Timing Parameters 352 Electrical Characteristics and AC Timing Parameters 2666 Through 3200 364 Timing Parameter Notes 376 Clock Specification 378 Definition for tCK AVG 378 Definition for tCK ABS 378 Definition for tCH AVG and tCL AVG 378 Definition for tJIT per and tJIT per,lck 378 Definition for tJIT cc and tJIT cc,lck 378 Definition for tERR nper 378 Jitter Notes 379 Converting Time-Based Specifications to Clock-Based Requirements 380 Options Tables 381 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2015 Micron Technology, Inc. All rights reserved. 8Gb x4, x8, x16 DDR4 SDRAM Features List of Figures Figure 1 Order Part Number Example 3 Figure 2 Gig x 4 Functional Block Diagram 21 Figure 3 1 Gig x 8 Functional Block Diagram 21 Figure 4 512 Meg x 16 Functional Block Diagram 22 Figure 5 78-Ball x4, x8 Ball Assignments 23 Figure 6 96-Ball x16 Ball Assignments 24 Figure 7 78-Ball FBGA x4, x8 PM 28 Figure 8 78-Ball FBGA x4, x8 WE 29 Figure 9 78-Ball FBGA x4, x8 SA 30 Figure 10 96-Ball FBGA x16 HA 31 Figure 11 96-Ball FBGA x16 JY 32 Figure 12 96-Ball FBGA x16 LY 33 Figure 13 Simplified State Diagram 34 Figure 14 RESET and Initialization Sequence at Power-On Ramping 40 Figure 15 RESET Procedure at Power Stable Condition 41 Figure 16 tMRD Timing 43 Figure 17 tMOD Timing 43 Figure 18 DLL-Off Mode Read Timing Operation 73 Figure 19 DLL Switch Sequence from DLL-On to DLL-Off 75 Figure 20 DLL Switch Sequence from DLL-Off to DLL-On 76 Figure 21 Write Leveling Concept, Example 1 78 Figure 22 Write Leveling Concept, Example 2 79 Figure 23 Write Leveling Sequence DQS Capturing CK LOW at T1 and CK HIGH at T2 80 Figure 24 Write Leveling Exit 81 Figure 25 CAL Timing Definition 82 Figure 26 CAL Timing Example Consecutive CS_n = LOW 82 Figure 27 CAL Enable Timing tMOD_CAL 83 Figure 28 tMOD_CAL, MRS to Valid Command Timing with CAL Enabled 83 Figure 29 CAL Enabling MRS to Next MRS Command, tMRD_CAL 84 Figure 30 tMRD_CAL, Mode Register Cycle Time With CAL Enabled 84 Figure 31 Consecutive READ BL8, CAL3, 1tCK Preamble, Different Bank Group 85 Figure 32 Consecutive READ BL8, CAL4, 1tCK Preamble, Different Bank Group 85 Figure 33 Auto Self Refresh Ranges 88 Figure 34 MPR Block Diagram 89 Figure 35 MPR READ Timing 96 Figure 36 MPR Back-to-Back READ Timing 96 Figure 37 MPR READ-to-WRITE Timing 97 Figure 38 MPR WRITE and WRITE-to-READ Timing 98 Figure 39 MPR Back-to-Back WRITE Timing 99 Figure 40 REFRESH Timing 99 Figure 41 READ-to-REFRESH Timing 100 Figure 42 WRITE-to-REFRESH Timing 100 Figure 43 Clock Mode Change from 1/2 Rate to 1/4 Rate Initialization 103 Figure 44 Clock Mode Change After Exiting Self Refresh 103 Figure 45 Comparison Between Gear-Down Disable and Gear-Down Enable 104 Figure 46 Maximum Power-Saving Mode Entry 105 Figure 47 Maximum Power-Saving Mode Entry with PDA 106 Figure 48 Maintaining Maximum Power-Saving Mode with CKE Transition 106 Figure 49 Maximum Power-Saving Mode Exit 107 Figure 50 Command/Address Parity Operation 108 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2015 Micron Technology, Inc. All rights reserved. 8Gb x4, x8, x16 DDR4 SDRAM Features Figure 51 Command/Address Parity During Normal Operation 110 Figure 52 Persistent CA Parity Error Checking Operation 111 Figure 53 CA Parity Error Checking SRE Attempt 111 Figure 54 CA Parity Error Checking SRX Attempt 112 Figure 55 CA Parity Error Checking PDE/PDX 112 Figure 56 Parity Entry Timing Example tMRD_PAR 113 Figure 57 Parity Entry Timing Example tMOD_PAR 113 Figure 58 Parity Exit Timing Example tMRD_PAR 114 Figure 59 Parity Exit Timing Example tMOD_PAR 114 Figure 60 CA Parity Flow Diagram 115 Figure 61 PDA Operation Enabled, BL8 117 Figure 62 PDA Operation Enabled, BC4 117 Figure 63 MRS PDA Exit 118 Figure 64 VREFDQ Voltage Range 119 Figure 65 Example of VREF Set Tolerance and Step Size 121 Figure 66 VREFDQ Timing Diagram for VREF,time Parameter 122 Figure 67 VREFDQ Training Mode Entry and Exit Timing Diagram 123 Figure 68 VREF Step Single Step Size Increment Case 124 Figure 69 VREF Step Single Step Size Decrement Case 124 Figure 70 VREF Full Step From VREF,min to VREF,maxCase 125 Figure 71 VREF Full Step From VREF,max to VREF,minCase 125 Figure 72 VREFDQ Equivalent Circuit 126 Figure 73 Connectivity Test Mode Entry 130 Figure 74 hPPR WRA Entry 135 Figure 75 hPPR WRA Repair and Exit 135 Figure 76 hPPR WR Entry 136 Figure 77 hPPR WR Repair and Exit 137 Figure 78 sPPR Entry 139 Figure 79 sPPR Repair, and Exit 140 Figure 80 tRRD Timing 141 Figure 81 tFAW Timing 141 Figure 82 REFRESH Command Timing 143 Figure 83 Postponing REFRESH Commands Example 143 Figure 84 Pulling In REFRESH Commands Example 143 Figure 85 TCR Mode Example1 145 Figure 86 4Gb with Fine Granularity Refresh Mode Example 148 Figure 87 OTF REFRESH Command Timing 149 Figure 88 Self Refresh Entry/Exit Timing 152 Figure 89 Self Refresh Entry/Exit Timing with CAL Mode 153 Figure 90 Self Refresh Abort 154 Figure 91 Self Refresh Exit with NOP Command 155 Figure 92 Active Power-Down Entry and Exit 157 Figure 93 Power-Down Entry After Read and Read with Auto Precharge 158 Figure 94 Power-Down Entry After Write and Write with Auto Precharge 158 Figure 95 Power-Down Entry After Write 159 Figure 96 Precharge Power-Down Entry and Exit 159 Figure 97 REFRESH Command to Power-Down Entry 160 Figure 98 Active Command to Power-Down Entry 160 Figure 99 PRECHARGE/PRECHARGE ALL Command to Power-Down Entry 161 Figure 100 MRS Command to Power-Down Entry 161 Figure 101 Power-Down Entry/Exit Clarifications Case 1 162 Figure 102 Active Power-Down Entry and Exit Timing with CAL 162 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2015 Micron Technology, Inc. All rights reserved. 8Gb x4, x8, x16 DDR4 SDRAM Features Figure 103 REFRESH Command to Power-Down Entry with CAL 163 Figure 104 ODT Power-Down Entry with ODT Buffer Disable Mode 164 Figure 105 ODT Power-Down Exit with ODT Buffer Disable Mode 165 Figure 106 CRC Write Data Operation 166 Figure 107 CRC Error Reporting 175 Figure 108 CA Parity Flow Diagram 176 Figure 109 1tCK vs. 2tCK WRITE Preamble Mode 181 Figure 110 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 4 182 Figure 111 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 5 183 Figure 112 1tCK vs. 2 tCK WRITE Preamble Mode, tCCD = 6 183 Figure 113 1tCK vs. 2tCK READ Preamble Mode 184 Figure 114 READ Preamble Training 185 Figure 115 WRITE Postamble 185 Figure 116 READ Postamble 186 Figure 117 Bank Group x4/x8 Block Diagram 187 Figure 118 READ Burst tCCD_S and tCCD_L Examples 188 Figure 119 Write Burst tCCD_S and tCCD_L Examples 188 Figure 120 tRRD Timing 189 Figure 121 tWTR_S Timing WRITE-to-READ, Different Bank Group, CRC and DM Disabled 189 Figure 122 tWTR_L Timing WRITE-to-READ, Same Bank Group, CRC and DM Disabled 190 Figure 123 Read Timing Definition 192 Figure 124 Clock-to-Data Strobe Relationship 193 Figure 125 Data Strobe-to-Data Relationship 194 Figure 126 tLZ and tHZ Method for Calculating Transitions and Endpoints 195 Figure 127 tRPRE Method for Calculating Transitions and Endpoints 196 Figure 128 tRPST Method for Calculating Transitions and Endpoints 197 Figure 129 READ Burst Operation, RL = 11 AL = 0, CL = 11, BL8 198 Figure 130 READ Burst Operation, RL = 21 AL = 10, CL = 11, BL8 199 Figure 131 Consecutive READ BL8 with 1tCK Preamble in Different Bank Group 200 Figure 132 Consecutive READ BL8 with 2tCK Preamble in Different Bank Group 200 Figure 133 Nonconsecutive READ BL8 with 1tCK Preamble in Same or Different Bank Group 201 Figure 134 Nonconsecutive READ BL8 with 2tCK Preamble in Same or Different Bank Group 201 Figure 135 READ BC4 to READ BC4 with 1tCK Preamble in Different Bank Group 202 Figure 136 READ BC4 to READ BC4 with 2tCK Preamble in Different Bank Group 202 Figure 137 READ BL8 to READ BC4 OTF with 1tCK Preamble in Different Bank Group 203 Figure 138 READ BL8 to READ BC4 OTF with 2tCK Preamble in Different Bank Group 203 Figure 139 READ BC4 to READ BL8 OTF with 1tCK Preamble in Different Bank Group 204 Figure 140 READ BC4 to READ BL8 OTF with 2tCK Preamble in Different Bank Group 204 Figure 141 READ BL8 to WRITE BL8 with 1tCK Preamble in Same or Different Bank Group 205 Figure 142 READ BL8 to WRITE BL8 with 2tCK Preamble in Same or Different Bank Group 205 Figure 143 READ BC4 OTF to WRITE BC4 OTF with 1tCK Preamble in Same or Different Bank Group 206 Figure 144 READ BC4 OTF to WRITE BC4 OTF with 2tCK Preamble in Same or Different Bank Group 207 Figure 145 READ BC4 Fixed to WRITE BC4 Fixed with 1tCK Preamble in Same or Different Bank Group 207 Figure 146 READ BC4 Fixed to WRITE BC4 Fixed with 2tCK Preamble in Same or Different Bank Group 208 Figure 147 READ BC4 to WRITE BL8 OTF with 1tCK Preamble in Same or Different Bank Group 209 Figure 148 READ BC4 to WRITE BL8 OTF with 2tCK Preamble in Same or Different Bank Group 209 Figure 149 READ BL8 to WRITE BC4 OTF with 1tCK Preamble in Same or Different Bank Group 210 Figure 150 READ BL8 to WRITE BC4 OTF with 2tCK Preamble in Same or Different Bank Group 210 Figure 151 READ to PRECHARGE with 1tCK Preamble 211 Figure 152 READ to PRECHARGE with 2tCK Preamble 212 Figure 153 READ to PRECHARGE with Additive Latency and 1tCK Preamble 212 Figure 154 READ with Auto Precharge and 1tCK Preamble 213 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2015 Micron Technology, Inc. All rights reserved. 8Gb x4, x8, x16 DDR4 SDRAM Features Figure 155 READ with Auto Precharge, Additive Latency, and 1tCK Preamble 214 Figure 156 Consecutive READ BL8 with 1tCK Preamble and DBI in Different Bank Group 214 Figure 157 Consecutive READ BL8 with 1tCK Preamble and CA Parity in Different Bank Group 215 Figure 158 READ BL8 to WRITE BL8 with 1tCK Preamble and CA Parity in Same or Different Bank Group 216 Figure 159 READ BL8 to WRITE BL8 or BC4 OTF with 1tCK Preamble and Write CRC in Same or Different Bank Group 217 Figure 160 READ BC4 Fixed to WRITE BC4 Fixed with 1tCK Preamble and Write CRC in Same or Different Bank Group 218 Figure 161 Consecutive READ BL8 with CAL 3tCK and 1tCK Preamble in Different Bank Group 218 Figure 162 Consecutive READ BL8 with CAL 4tCK and 1tCK Preamble in Different Bank Group 219 Burst type BT Data burst ordering within a READ or WRITE burst access 0 = Nibble sequential 1 = Interleave Burst length BL Data burst size associated with each read or write access 00 = BL8 fixed 01 = BC4 or BL8 on-the-fly 10 = BC4 fixed 11 = Reserved Notes Not allowed when 1/4 rate gear-down mode is enabled. If WR requirement exceeds 28 clocks or RTP exceeds 14 clocks, WR should be set to 28 clocks and RTP should be set to 14 clocks. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2015 Micron Technology, Inc. All rights reserved. 8Gb x4, x8, x16 DDR4 SDRAM Mode Register 0 Burst Length, Type, and Order Accesses within a given burst may be programmed to sequential or interleaved order. The ordering of accesses within a burst is determined by the burst length, burst type, and the starting column address as shown in the following table. Burst length options include fixed BC4, fixed BL8, and on-the-fly OTF , which allows BC4 or BL8 to be selected coincidentally with the registration of a READ or WRITE command via A12/BC_n. Table 8 Burst Type and Burst Order Note 1 applies to the entire table Starting Burst Length READ/ Column Address WRITE A[2, 1, 0] READ WRITE 0, V, V 1, V, V READ WRITE V, V, V Burst Type = Sequential Decimal 0, 1, 2, 3, T, T, T, T 1, 2, 3, 0, T, T, T, T 2, 3, 0, 1, T, T, T, T 3, 0, 1, 2, T, T, T, T 4, 5, 6, 7, T, T, T, T 5, 6, 7, 4, T, T, T, T 6, 7, 4, 5, T, T, T, T 7, 4, 5, 6, T, T, T, T 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 Burst Type = Interleaved Decimal 0, 1, 2, 3, T, T, T, T 1, 0, 3, 2, T, T, T, T 2, 3, 0, 1, T, T, T, T 3, 2, 1, 0, T, T, T, T 4, 5, 6, 7, T, T, T, T 5, 4, 7, 6, T, T, T, T 6, 7, 4, 5, T, T, T, T 7, 6, 5, 4, T, T, T, T 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7 Notes 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 bit number is the value of CA[2:0] that causes this bit to be the first read during a burst. When setting burst length to BC4 fixed in MR0, the internal WRITE operation starts two clock cycles earlier than for the BL8 mode, meaning the starting point for tWR and tWTR will be pulled in by two clocks. When setting burst length to OTF in MR0, the internal WRITE operation starts at the same time as a BL8 even if BC4 was selected during column time using A12/BC4_n meaning that if the OTF MR0 setting is used, the starting point for tWR and tWTR will not be pulled in by two clocks as described in the BC4 fixed case. T = Output driver for data and strobes are in High-Z. V = Valid logic level 0 or 1 , but respective buffer input ignores level on input pins. X = “Don’t Care.” Micron Technology, Inc. reserves the right to change products or specifications without notice. 2015 Micron Technology, Inc. All rights reserved. 8Gb x4, x8, x16 DDR4 SDRAM Mode Register 0 CAS Latency The CAS latency CL setting is defined in the MR0 Register Definition table. CAS latency is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The device does not support half-clock latencies. The overall read latency RL is defined as additive latency AL + CAS latency CL RL = AL + CL. Test Mode The normal operating mode is selected by MR0[7] and all other bits set to the desired values shown in the MR0 Register Definition table. Programming MR0[7] to a value of 1 places the device into a DRAM manufacturer-defined test mode to be used only by the manufacturer, not by the end user. No operations or functionality is specified if MR0[7] = Write Recovery WR /READ-to-PRECHARGE The programmed write recovery WR value is used for the auto precharge feature along with tRP to determine tDAL. WR for auto precharge MIN in clock cycles is calculated by dividing tWR in ns by tCK in ns and rounding up to the next integer WR MIN cycles = roundup tWR[ns]/tCK[ns] . The WR value must be programmed to be equal to or larger than tWR MIN . When both DM and write CRC are enabled in the mode register, the device calculates CRC before sending the write data into the array tWR values will change when enabled. If there is a CRC error, the device blocks the WRITE operation and discards the data. Internal READ-to-PRECHARGE RTP command delay for auto precharge MIN in clock cycles is calculated by dividing tRTP in ns by tCK in ns and rounding up to the next integer RTP MIN cycles = roundup tRTP[ns]/tCK[ns] . The RTP value in the mode register must be programmed to be equal to or larger than RTP MIN . The programmed RTP value is used with tRP to determine the ACT timing to the same bank. DLL RESET The DLL reset bit is self-clearing, meaning that it returns to the value of 0 after the DLL RESET function has been issued. After the DLL is enabled, a subsequent DLL RESET should be applied. Any time the DLL RESET function is used, tDLLK must be met before functions requiring the DLL can be used, such as READ commands or synchronous ODT operations, for example, . Micron Technology, Inc. reserves the right to change products or specifications without notice. 2015 Micron Technology, Inc. All rights reserved. 8Gb x4, x8, x16 DDR4 SDRAM Mode Register 1 Mode Register 1 Mode register 1 MR1 controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die only settings required for speed bin support are available. MR1 is written by issuing the MRS command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR1 Register Definition table. Table 9 Address Pin Mapping Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Mode 21 20 19 18 17 13 12 11 10 9 8 7 6 5 4 3 2 1 0 register Burst Ordering for BL8 DDR4 supports fixed WRITE burst ordering [A2:A1:A0 = 0:0:0] when write CRC is enabled in BL8 fixed . CRC Data Bit Mapping Table 54 CRC Data Mapping for x4 Devices, BL8 Func- Transfer tion DQ0 D0 DQ1 D8 D9 D10 D11 D12 D13 D14 DQ2 D16 D17 D18 D19 D20 D21 D22 DQ3 D24 D25 D26 D27 D28 D29 D30 D7 CRC0 CRC4 D15 CRC1 CRC5 D23 CRC2 CRC6 D31 CRC3 CRC7 Table 55 CRC Data Mapping for x8 Devices, BL8 Func- Transfer tion DQ0 D0 D7 CRC0 1 DQ1 D8 D9 D10 D11 D12 D13 D14 D15 CRC1 1 DQ2 D16 D17 D18 D19 D20 D21 D22 D23 CRC2 1 DQ3 D24 D25 D26 D27 D28 D29 D30 D31 CRC3 1 DQ4 D32 D33 D34 D35 D36 D37 D38 D39 CRC4 1 DQ5 D40 D41 D42 D43 D44 D45 D46 D47 CRC5 1 DQ6 D48 D49 D50 D51 D52 D53 D54 D55 CRC6 1 DQ7 D56 D57 D58 D59 D60 D61 D62 D63 CRC7 1 DM_n/ D64 D65 D66 D67 D68 D69 D70 D71 DBI_n A x16 device is treated as two x8 devices a x16 device will have two identical CRC trees implemented. CRC[7:0] covers data bits D[71:0], and CRC[15:8] covers data bits D[143:72]. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2015 Micron Technology, Inc. All rights reserved. 8Gb x4, x8, x16 DDR4 SDRAM CRC Write Data Feature Table 56 CRC Data Mapping for x16 Devices, BL8 Func- Transfer tion DQ0 D0 D7 CRC0 1 DQ1 D8

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8Gb x4, x8, x16 DDR4 SDRAM Features

DDR4 SDRAM

MT40A2G4 MT40A1G8 MT40A512M16
• VDD = VDDQ = 1.2V ±60mV
• VPP = 2.5V, +250mV
• On-die, internal, adjustable VREFDQ generation
• 1.2V pseudo open-drain I/O
• TC maximum up to 95°C
64ms, 8192-cycle refresh up to 85°C 32ms, 8192-cycle refresh at >85°C to 95°C
• 16 internal banks x4, x8 4 groups of 4 banks each
• 8 internal banks x16 2 groups of 4 banks each
• 8n-bit prefetch architecture
• Programmable data strobe preambles
• Data strobe preamble training
• Command/Address latency CAL
• Multipurpose register READ and WRITE capability
• Write and read leveling
• Self refresh mode
• Low-power auto self refresh LPASR
• Temperature controlled refresh TCR
• Fine granularity refresh
• Self refresh abort
• Maximum power saving
• Output driver calibration
• Nominal, park, and dynamic on-die termination ODT
• Data bus inversion DBI for data bus
• Command/Address CA parity
• Databus write cyclic redundancy check CRC
• Per-DRAM addressability
• Connectivity test x16
• JEDEC JESD-79-4 compliant
• sPPR and hPPR capability

Options1
• Configuration 2 Gig x 4 1 Gig x 8 512 Meg x 16
• Timing cycle time 0.625ns CL = 22 DDR4-3200 0.682ns CL = 21 DDR4-2933 0.750ns CL = 19 DDR4-2666 0.750ns CL = 18 DDR4-2666 0.833ns CL = 17 DDR4-2400 0.833ns CL = 16 DDR4-2400 0.937ns CL = 15 DDR4-2133 1.071ns CL = 13 DDR4-1866
• Operating temperature Commercial 0° TC 95°C Industrial TC 95°C

Marking
2G4 1G8 512M16

PM WE SA

HA JY LY
-062E -068 -075 -075E -083 -083E -093E -107E

None IT :A,
:B, :D, :G, :E, :H

Note:

Not all options listed can be combined to define an offered product. Use the part catalog search on for available offerings.

Table 1 Key Timing Parameters

Speed Grade -062E6 -0685 -0754 -075E4

Data Rate MT/s 3200 2933 2666

Target CL-tRCD-tRP 22-22-22 21-21-21 19-19-19 18-18-18

CL ns
tRCD ns
tRP ns

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Products and specifications discussed herein are subject to change by Micron without notice.
8Gb x4, x8, x16 DDR4 SDRAM Features

Table 1 Key Timing Parameters Continued

Speed Grade -0833 -083E3 -093E2 -107E1

Data Rate MT/s 2400 2133 1866

Target CL-tRCD-tRP 17-17-17 16-16-16 15-15-15 13-13-13

CL ns
tRCD ns
tRP ns

Backward compatible to 1600, CL = Backward compatible to 1600, CL = 11 and 1866, CL = Backward compatible to 1600, CL = 11 1866, CL = 13 and 2133, CL = Backward compatible to 1600, CL = 11 1866, CL = 13 2133, CL = 15 and 2400, CL = Backward compatible to 1600, CL = 11 1866, CL = 13 2133, CL = 15 2400, CL = 17 and 2666, CL = Speed
offering may have restricted availability. Backward compatible to 1600, CL = 11 1866, CL = 13 2133, CL = 15 2400, CL = 17 2666, CL = Speed
offering may have restricted availability.

Table 2 Addressing

Parameter Number of bank groups Bank group address Bank count per group Bank address in bank group Row addressing Column addressing Page size1
2048 Meg x 4
VREFDQ Range and Levels 120 VREFDQ Step Size 120 VREFDQ Increment and Decrement Timing 121 VREFDQ Target Settings 125 Connectivity Test Mode 127 Pin Mapping 127 Minimum Terms Definition for Logic Equations 128 Logic Equations for a x4 Device 128 Logic Equations for a x8 Device 129 Logic Equations for a x16 Device 129 CT Input Timing Requirements 129 Excessive Row Activation 131 Post Package Repair 132 Post Package Repair 132 Hard Post Package Repair 133 hPPR Row Repair - Entry 133 hPPR Row Repair WRA Initiated REF Commands Allowed 133 hPPR Row Repair WR Initiated REF Commands NOT Allowed 135 sPPR Row Repair 137 hPPR/sPPR Support Identifier 140 ACTIVATE Command 140 PRECHARGE Command 141 REFRESH Command 142 Temperature-Controlled Refresh Mode 144 TCR Mode Normal Temperature Range 144 TCR Mode Extended Temperature Range 144 Fine Granularity Refresh Mode 146 Mode Register and Command Truth Table 146 tREFI and tRFC Parameters 146 Changing Refresh Rate 149 Usage with TCR Mode 149 Self Refresh Entry and Exit 149 SELF REFRESH Operation 151 Self Refresh Abort 153 Self Refresh Exit with NOP Command 154 Power-Down Mode 156 Power-Down Clarifications Case 1 161 Power-Down Entry, Exit Timing with CAL 162 ODT Input Buffer Disable Mode for Power-Down 164 CRC Write Data Feature 166 CRC Write Data 166 WRITE CRC DATA Operation 166 DBI_n and CRC Both Enabled 167 DM_n and CRC Both Enabled 167 DM_n and DBI_n Conflict During Writes with CRC Enabled 167 CRC and Write Preamble Restrictions 167 CRC Simultaneous Operation Restrictions 167 CRC Polynomial 167 CRC Combinatorial Logic Equations 168 Burst Ordering for BL8 169 CRC Data Bit Mapping 169 CRC Enabled With BC4 170

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8Gb x4, x8, x16 DDR4 SDRAM Features

CRC with BC4 Data Bit Mapping 170 CRC Equations for x8 Device in BC4 Mode with A2 = 0 and A2 = 1 173 CRC Error Handling 175 CRC Write Data Flow Diagram 176 Data Bus Inversion 177 DBI During a WRITE Operation 177 DBI During a READ Operation 178 Data Mask 179 Programmable Preamble Modes and DQS Postambles 181 WRITE Preamble Mode 181 READ Preamble Mode 184 READ Preamble Training 184 WRITE Postamble 185 READ Postamble 185 Bank Access Operation 187 READ Operation 191 Read Timing Definitions 191 Read Timing Clock-to-Data Strobe Relationship 192 Read Timing Data Strobe-to-Data Relationship 194 tLZ DQS , tLZ DQ , tHZ DQS , and tHZ DQ Calculations 195 tRPRE Calculation 196 tRPST Calculation 197 READ Burst Operation 198 READ Operation Followed by Another READ Operation 200 READ Operation Followed by WRITE Operation 205 READ Operation Followed by PRECHARGE Operation 211 READ Operation with Read Data Bus Inversion DBI 214 READ Operation with Command/Address Parity CA Parity 215 READ Followed by WRITE with CRC Enabled 217 READ Operation with Command/Address Latency CAL Enabled 218 WRITE Operation 220 Write Timing Definitions 220 Write Timing Clock-to-Data Strobe Relationship 220 tWPRE Calculation 222 tWPST Calculation 223 Write Timing Data Strobe-to-Data Relationship 223 WRITE Burst Operation 227 WRITE Operation Followed by Another WRITE Operation 229 WRITE Operation Followed by READ Operation 235 WRITE Operation Followed by PRECHARGE Operation 239 WRITE Operation with WRITE DBI Enabled 242 WRITE Operation with CA Parity Enabled 244 WRITE Operation with Write CRC Enabled 245 Write Timing Violations 250 Motivation 250 Data Setup and Hold Violations 250 Strobe-to-Strobe and Strobe-to-Clock Violations 250 ZQ CALIBRATION Commands 251 On-Die Termination 253 ODT Mode Register and ODT State Table 253 ODT Read Disable State Table 254 Synchronous ODT Mode 255

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8Gb x4, x8, x16 DDR4 SDRAM Features

ODT Latency and Posted ODT 255 Timing Parameters 255 ODT During Reads 257 Dynamic ODT 258 Functional Description 258 Asynchronous ODT Mode 261 Electrical Specifications 262 Absolute Ratings 262 DRAM Component Operating Temperature Range 262 Electrical Characteristics AC and DC Operating Conditions 263 Supply Operating Conditions 263 Leakages 264 VREFCA Supply 264 VREFDQ Supply and Calibration Ranges 265 VREFDQ Ranges 266 Electrical Characteristics AC and DC Single-Ended Input Measurement Levels 267 RESET_n Input Levels 267 Command/Address Input Levels 267 Command, Control, and Address Setup, Hold, and Derating 269 Data Receiver Input Requirements 271 Connectivity Test CT Mode Input Levels 275 Electrical Characteristics AC and DC Differential Input Measurement Levels 279 Differential Inputs 279 Single-Ended Requirements for CK Differential Signals 280 Slew Rate Definitions for CK Differential Input Signals 281 CK Differential Input Cross Point Voltage 282 DQS Differential Input Signal Definition and Swing Requirements 284 DQS Differential Input Cross Point Voltage 286 Slew Rate Definitions for DQS Differential Input Signals 287 Electrical Characteristics Overshoot and Undershoot Specifications 289 Address, Command, and Control Overshoot and Undershoot Specifications 289 Clock Overshoot and Undershoot Specifications 289 Data, Strobe, and Mask Overshoot and Undershoot Specifications 290 Electrical Characteristics AC and DC Output Measurement Levels 291 Single-Ended Outputs 291 Differential Outputs 292 Reference Load for AC Timing and Output Slew Rate 294 Connectivity Test Mode Output Levels 294 Electrical Characteristics AC and DC Output Driver Characteristics 296 Connectivity Test Mode Output Driver Electrical Characteristics 296 Output Driver Electrical Characteristics 297 Output Driver Temperature and Voltage Sensitivity 300 Alert Driver 300 Electrical Characteristics On-Die Termination Characteristics 302 ODT Levels and I-V Characteristics 302 ODT Temperature and Voltage Sensitivity 303 ODT Timing Definitions 304 DRAM Package Electrical Specifications 307 Thermal Characteristics 311 Current Specifications Measurement Conditions 312 IDD, IPP, and IDDQ Measurement Conditions 312 IDD Definitions 314

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8Gb x4, x8, x16 DDR4 SDRAM Features

Current Specifications Patterns and Test Conditions 318 Current Test Definitions and Patterns 318 IDD Specifications 327

Current Specifications Limits 328 Speed Bin Tables 342 Refresh Parameters By Device Density 351 Electrical Characteristics and AC Timing Parameters 352 Electrical Characteristics and AC Timing Parameters 2666 Through 3200 364 Timing Parameter Notes 376 Clock Specification 378

Definition for tCK AVG 378 Definition for tCK ABS 378 Definition for tCH AVG and tCL AVG 378 Definition for tJIT per and tJIT per,lck 378 Definition for tJIT cc and tJIT cc,lck 378 Definition for tERR nper 378 Jitter Notes 379 Converting Time-Based Specifications to Clock-Based Requirements 380 Options Tables 381

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8Gb x4, x8, x16 DDR4 SDRAM Features

List of Figures

Figure 1 Order Part Number Example 3 Figure 2 Gig x 4 Functional Block Diagram 21 Figure 3 1 Gig x 8 Functional Block Diagram 21 Figure 4 512 Meg x 16 Functional Block Diagram 22 Figure 5 78-Ball x4, x8 Ball Assignments 23 Figure 6 96-Ball x16 Ball Assignments 24 Figure 7 78-Ball FBGA x4, x8 PM 28 Figure 8 78-Ball FBGA x4, x8 WE 29 Figure 9 78-Ball FBGA x4, x8 SA 30 Figure 10 96-Ball FBGA x16 HA 31 Figure 11 96-Ball FBGA x16 JY 32 Figure 12 96-Ball FBGA x16 LY 33 Figure 13 Simplified State Diagram 34 Figure 14 RESET and Initialization Sequence at Power-On Ramping 40 Figure 15 RESET Procedure at Power Stable Condition 41 Figure 16 tMRD Timing 43 Figure 17 tMOD Timing 43 Figure 18 DLL-Off Mode Read Timing Operation 73 Figure 19 DLL Switch Sequence from DLL-On to DLL-Off 75 Figure 20 DLL Switch Sequence from DLL-Off to DLL-On 76 Figure 21 Write Leveling Concept, Example 1 78 Figure 22 Write Leveling Concept, Example 2 79 Figure 23 Write Leveling Sequence DQS Capturing CK LOW at T1 and CK HIGH at T2 80 Figure 24 Write Leveling Exit 81 Figure 25 CAL Timing Definition 82 Figure 26 CAL Timing Example Consecutive CS_n = LOW 82 Figure 27 CAL Enable Timing tMOD_CAL 83 Figure 28 tMOD_CAL, MRS to Valid Command Timing with CAL Enabled 83 Figure 29 CAL Enabling MRS to Next MRS Command, tMRD_CAL 84 Figure 30 tMRD_CAL, Mode Register Cycle Time With CAL Enabled 84 Figure 31 Consecutive READ BL8, CAL3, 1tCK Preamble, Different Bank Group 85 Figure 32 Consecutive READ BL8, CAL4, 1tCK Preamble, Different Bank Group 85 Figure 33 Auto Self Refresh Ranges 88 Figure 34 MPR Block Diagram 89 Figure 35 MPR READ Timing 96 Figure 36 MPR Back-to-Back READ Timing 96 Figure 37 MPR READ-to-WRITE Timing 97 Figure 38 MPR WRITE and WRITE-to-READ Timing 98 Figure 39 MPR Back-to-Back WRITE Timing 99 Figure 40 REFRESH Timing 99 Figure 41 READ-to-REFRESH Timing 100 Figure 42 WRITE-to-REFRESH Timing 100 Figure 43 Clock Mode Change from 1/2 Rate to 1/4 Rate Initialization 103 Figure 44 Clock Mode Change After Exiting Self Refresh 103 Figure 45 Comparison Between Gear-Down Disable and Gear-Down Enable 104 Figure 46 Maximum Power-Saving Mode Entry 105 Figure 47 Maximum Power-Saving Mode Entry with PDA 106 Figure 48 Maintaining Maximum Power-Saving Mode with CKE Transition 106 Figure 49 Maximum Power-Saving Mode Exit 107 Figure 50 Command/Address Parity Operation 108

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8Gb x4, x8, x16 DDR4 SDRAM Features

Figure 51 Command/Address Parity During Normal Operation 110 Figure 52 Persistent CA Parity Error Checking Operation 111 Figure 53 CA Parity Error Checking SRE Attempt 111 Figure 54 CA Parity Error Checking SRX Attempt 112 Figure 55 CA Parity Error Checking PDE/PDX 112 Figure 56 Parity Entry Timing Example tMRD_PAR 113 Figure 57 Parity Entry Timing Example tMOD_PAR 113 Figure 58 Parity Exit Timing Example tMRD_PAR 114 Figure 59 Parity Exit Timing Example tMOD_PAR 114 Figure 60 CA Parity Flow Diagram 115 Figure 61 PDA Operation Enabled, BL8 117 Figure 62 PDA Operation Enabled, BC4 117 Figure 63 MRS PDA Exit 118 Figure 64 VREFDQ Voltage Range 119 Figure 65 Example of VREF Set Tolerance and Step Size 121 Figure 66 VREFDQ Timing Diagram for VREF,time Parameter 122 Figure 67 VREFDQ Training Mode Entry and Exit Timing Diagram 123 Figure 68 VREF Step Single Step Size Increment Case 124 Figure 69 VREF Step Single Step Size Decrement Case 124 Figure 70 VREF Full Step From VREF,min to VREF,maxCase 125 Figure 71 VREF Full Step From VREF,max to VREF,minCase 125 Figure 72 VREFDQ Equivalent Circuit 126 Figure 73 Connectivity Test Mode Entry 130 Figure 74 hPPR WRA Entry 135 Figure 75 hPPR WRA Repair and Exit 135 Figure 76 hPPR WR Entry 136 Figure 77 hPPR WR Repair and Exit 137 Figure 78 sPPR Entry 139 Figure 79 sPPR Repair, and Exit 140 Figure 80 tRRD Timing 141 Figure 81 tFAW Timing 141 Figure 82 REFRESH Command Timing 143 Figure 83 Postponing REFRESH Commands Example 143 Figure 84 Pulling In REFRESH Commands Example 143 Figure 85 TCR Mode Example1 145 Figure 86 4Gb with Fine Granularity Refresh Mode Example 148 Figure 87 OTF REFRESH Command Timing 149 Figure 88 Self Refresh Entry/Exit Timing 152 Figure 89 Self Refresh Entry/Exit Timing with CAL Mode 153 Figure 90 Self Refresh Abort 154 Figure 91 Self Refresh Exit with NOP Command 155 Figure 92 Active Power-Down Entry and Exit 157 Figure 93 Power-Down Entry After Read and Read with Auto Precharge 158 Figure 94 Power-Down Entry After Write and Write with Auto Precharge 158 Figure 95 Power-Down Entry After Write 159 Figure 96 Precharge Power-Down Entry and Exit 159 Figure 97 REFRESH Command to Power-Down Entry 160 Figure 98 Active Command to Power-Down Entry 160 Figure 99 PRECHARGE/PRECHARGE ALL Command to Power-Down Entry 161 Figure 100 MRS Command to Power-Down Entry 161 Figure 101 Power-Down Entry/Exit Clarifications Case 1 162 Figure 102 Active Power-Down Entry and Exit Timing with CAL 162

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8Gb x4, x8, x16 DDR4 SDRAM Features

Figure 103 REFRESH Command to Power-Down Entry with CAL 163

Figure 104 ODT Power-Down Entry with ODT Buffer Disable Mode 164

Figure 105 ODT Power-Down Exit with ODT Buffer Disable Mode 165

Figure 106 CRC Write Data Operation 166

Figure 107 CRC Error Reporting 175

Figure 108 CA Parity Flow Diagram 176 Figure 109 1tCK vs. 2tCK WRITE Preamble Mode 181 Figure 110 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 4 182 Figure 111 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 5 183 Figure 112 1tCK vs. 2 tCK WRITE Preamble Mode, tCCD = 6 183 Figure 113 1tCK vs. 2tCK READ Preamble Mode 184

Figure 114 READ Preamble Training 185

Figure 115 WRITE Postamble 185

Figure 116 READ Postamble 186

Figure 117 Bank Group x4/x8 Block Diagram 187 Figure 118 READ Burst tCCD_S and tCCD_L Examples 188 Figure 119 Write Burst tCCD_S and tCCD_L Examples 188 Figure 120 tRRD Timing 189 Figure 121 tWTR_S Timing WRITE-to-READ, Different Bank Group, CRC and DM Disabled 189 Figure 122 tWTR_L Timing WRITE-to-READ, Same Bank Group, CRC and DM Disabled 190

Figure 123 Read Timing Definition 192

Figure 124 Clock-to-Data Strobe Relationship 193

Figure 125 Data Strobe-to-Data Relationship 194 Figure 126 tLZ and tHZ Method for Calculating Transitions and Endpoints 195 Figure 127 tRPRE Method for Calculating Transitions and Endpoints 196 Figure 128 tRPST Method for Calculating Transitions and Endpoints 197

Figure 129 READ Burst Operation, RL = 11 AL = 0, CL = 11, BL8 198

Figure 130 READ Burst Operation, RL = 21 AL = 10, CL = 11, BL8 199 Figure 131 Consecutive READ BL8 with 1tCK Preamble in Different Bank Group 200 Figure 132 Consecutive READ BL8 with 2tCK Preamble in Different Bank Group 200 Figure 133 Nonconsecutive READ BL8 with 1tCK Preamble in Same or Different Bank Group 201 Figure 134 Nonconsecutive READ BL8 with 2tCK Preamble in Same or Different Bank Group 201 Figure 135 READ BC4 to READ BC4 with 1tCK Preamble in Different Bank Group 202 Figure 136 READ BC4 to READ BC4 with 2tCK Preamble in Different Bank Group 202 Figure 137 READ BL8 to READ BC4 OTF with 1tCK Preamble in Different Bank Group 203 Figure 138 READ BL8 to READ BC4 OTF with 2tCK Preamble in Different Bank Group 203 Figure 139 READ BC4 to READ BL8 OTF with 1tCK Preamble in Different Bank Group 204 Figure 140 READ BC4 to READ BL8 OTF with 2tCK Preamble in Different Bank Group 204 Figure 141 READ BL8 to WRITE BL8 with 1tCK Preamble in Same or Different Bank Group 205 Figure 142 READ BL8 to WRITE BL8 with 2tCK Preamble in Same or Different Bank Group 205 Figure 143 READ BC4 OTF to WRITE BC4 OTF with 1tCK Preamble in Same or Different Bank Group 206 Figure 144 READ BC4 OTF to WRITE BC4 OTF with 2tCK Preamble in Same or Different Bank Group 207 Figure 145 READ BC4 Fixed to WRITE BC4 Fixed with 1tCK Preamble in Same or Different Bank Group 207 Figure 146 READ BC4 Fixed to WRITE BC4 Fixed with 2tCK Preamble in Same or Different Bank Group 208 Figure 147 READ BC4 to WRITE BL8 OTF with 1tCK Preamble in Same or Different Bank Group 209 Figure 148 READ BC4 to WRITE BL8 OTF with 2tCK Preamble in Same or Different Bank Group 209 Figure 149 READ BL8 to WRITE BC4 OTF with 1tCK Preamble in Same or Different Bank Group 210 Figure 150 READ BL8 to WRITE BC4 OTF with 2tCK Preamble in Same or Different Bank Group 210 Figure 151 READ to PRECHARGE with 1tCK Preamble 211 Figure 152 READ to PRECHARGE with 2tCK Preamble 212 Figure 153 READ to PRECHARGE with Additive Latency and 1tCK Preamble 212 Figure 154 READ with Auto Precharge and 1tCK Preamble 213

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8Gb x4, x8, x16 DDR4 SDRAM Features

Figure 155 READ with Auto Precharge, Additive Latency, and 1tCK Preamble 214 Figure 156 Consecutive READ BL8 with 1tCK Preamble and DBI in Different Bank Group 214 Figure 157 Consecutive READ BL8 with 1tCK Preamble and CA Parity in Different Bank Group 215 Figure 158 READ BL8 to WRITE BL8 with 1tCK Preamble and CA Parity in Same or Different Bank Group 216 Figure 159 READ BL8 to WRITE BL8 or BC4 OTF with 1tCK Preamble and Write CRC in Same or Different

Bank Group 217 Figure 160 READ BC4 Fixed to WRITE BC4 Fixed with 1tCK Preamble and Write CRC in Same or Different

Bank Group 218 Figure 161 Consecutive READ BL8 with CAL 3tCK and 1tCK Preamble in Different Bank Group 218 Figure 162 Consecutive READ BL8 with CAL 4tCK and 1tCK Preamble in Different Bank Group 219
Burst type BT Data burst ordering within a READ or WRITE burst access 0 = Nibble sequential 1 = Interleave

Burst length BL Data burst size associated with each read or write access 00 = BL8 fixed 01 = BC4 or BL8 on-the-fly 10 = BC4 fixed 11 = Reserved

Notes Not allowed when 1/4 rate gear-down mode is enabled. If WR requirement exceeds 28 clocks or RTP exceeds 14 clocks, WR should be set to 28 clocks and RTP should be set to 14 clocks.

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8Gb x4, x8, x16 DDR4 SDRAM Mode Register 0

Burst Length, Type, and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The ordering of accesses within a burst is determined by the burst length, burst type, and the starting column address as shown in the following table. Burst length options include fixed BC4, fixed BL8, and on-the-fly OTF , which allows BC4 or BL8 to be selected coincidentally with the registration of a READ or WRITE command via A12/BC_n.

Table 8 Burst Type and Burst Order

Note 1 applies to the entire table

Starting

Burst Length

READ/ Column Address

WRITE

A[2, 1, 0]

READ

WRITE
0, V, V
1, V, V

READ

WRITE

V, V, V

Burst Type = Sequential Decimal
0, 1, 2, 3, T, T, T, T 1, 2, 3, 0, T, T, T, T 2, 3, 0, 1, T, T, T, T 3, 0, 1, 2, T, T, T, T 4, 5, 6, 7, T, T, T, T 5, 6, 7, 4, T, T, T, T 6, 7, 4, 5, T, T, T, T 7, 4, 5, 6, T, T, T, T 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7

Burst Type = Interleaved Decimal
0, 1, 2, 3, T, T, T, T 1, 0, 3, 2, T, T, T, T 2, 3, 0, 1, T, T, T, T 3, 2, 1, 0, T, T, T, T 4, 5, 6, 7, T, T, T, T 5, 4, 7, 6, T, T, T, T 6, 7, 4, 5, T, T, T, T 7, 6, 5, 4, T, T, T, T 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7

Notes 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3
bit number is the value of CA[2:0] that causes this bit to be the first read during a burst.

When setting burst length to BC4 fixed in MR0, the internal WRITE operation starts two clock cycles earlier than for the BL8 mode, meaning the starting point for tWR and tWTR will be pulled in by two clocks. When setting burst length to OTF in MR0, the internal WRITE operation starts at the same time as a BL8 even if BC4 was selected during column time using A12/BC4_n meaning that if the OTF MR0 setting is used, the starting point for tWR and tWTR will not be pulled in by two clocks as described in the BC4 fixed case.

T = Output driver for data and strobes are in High-Z. V = Valid logic level 0 or 1 , but respective buffer input ignores level on input pins. X = “Don’t Care.”

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8Gb x4, x8, x16 DDR4 SDRAM Mode Register 0

CAS Latency

The CAS latency CL setting is defined in the MR0 Register Definition table. CAS latency is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The device does not support half-clock latencies. The overall read latency RL is defined as additive latency AL + CAS latency CL RL = AL + CL.

Test Mode

The normal operating mode is selected by MR0[7] and all other bits set to the desired values shown in the MR0 Register Definition table. Programming MR0[7] to a value of 1 places the device into a DRAM manufacturer-defined test mode to be used only by the manufacturer, not by the end user. No operations or functionality is specified if MR0[7] =

Write Recovery WR /READ-to-PRECHARGE

The programmed write recovery WR value is used for the auto precharge feature along with tRP to determine tDAL. WR for auto precharge MIN in clock cycles is calculated by dividing tWR in ns by tCK in ns and rounding up to the next integer WR MIN cycles = roundup tWR[ns]/tCK[ns] . The WR value must be programmed to be equal to or larger than tWR MIN . When both DM and write CRC are enabled in the mode register, the device calculates CRC before sending the write data into the array tWR values will change when enabled. If there is a CRC error, the device blocks the WRITE operation and discards the data.

Internal READ-to-PRECHARGE RTP command delay for auto precharge MIN in clock cycles is calculated by dividing tRTP in ns by tCK in ns and rounding up to the next integer RTP MIN cycles = roundup tRTP[ns]/tCK[ns] . The RTP value in the mode register must be programmed to be equal to or larger than RTP MIN . The programmed RTP value is used with tRP to determine the ACT timing to the same bank.

DLL RESET

The DLL reset bit is self-clearing, meaning that it returns to the value of 0 after the DLL RESET function has been issued. After the DLL is enabled, a subsequent DLL RESET should be applied. Any time the DLL RESET function is used, tDLLK must be met before functions requiring the DLL can be used, such as READ commands or synchronous ODT operations, for example, .

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8Gb x4, x8, x16 DDR4 SDRAM Mode Register 1

Mode Register 1

Mode register 1 MR1 controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die only settings required for speed bin support are available. MR1 is written by issuing the MRS command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR1 Register Definition table.

Table 9 Address Pin Mapping

Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Mode 21 20 19 18 17 13 12 11 10 9 8 7 6 5 4 3 2 1 0 register
Burst Ordering for BL8
DDR4 supports fixed WRITE burst ordering [A2:A1:A0 = 0:0:0] when write CRC is enabled in BL8 fixed .

CRC Data Bit Mapping

Table 54 CRC Data Mapping for x4 Devices, BL8

Func-

Transfer
tion

DQ0 D0

DQ1 D8

D9 D10 D11 D12 D13 D14

DQ2 D16 D17 D18 D19 D20 D21 D22

DQ3 D24 D25 D26 D27 D28 D29 D30

D7 CRC0 CRC4

D15 CRC1 CRC5

D23 CRC2 CRC6

D31 CRC3 CRC7

Table 55 CRC Data Mapping for x8 Devices, BL8

Func-

Transfer
tion

DQ0 D0

D7 CRC0 1

DQ1 D8

D9 D10 D11 D12 D13 D14 D15 CRC1 1

DQ2 D16 D17 D18 D19 D20 D21 D22 D23 CRC2 1

DQ3 D24 D25 D26 D27 D28 D29 D30 D31 CRC3 1

DQ4 D32 D33 D34 D35 D36 D37 D38 D39 CRC4 1

DQ5 D40 D41 D42 D43 D44 D45 D46 D47 CRC5 1

DQ6 D48 D49 D50 D51 D52 D53 D54 D55 CRC6 1

DQ7 D56 D57 D58 D59 D60 D61 D62 D63 CRC7 1

DM_n/ D64 D65 D66 D67 D68 D69 D70 D71

DBI_n

A x16 device is treated as two x8 devices a x16 device will have two identical CRC trees implemented. CRC[7:0] covers data bits D[71:0], and CRC[15:8] covers data bits D[143:72].

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8Gb x4, x8, x16 DDR4 SDRAM CRC Write Data Feature

Table 56 CRC Data Mapping for x16 Devices, BL8

Func-

Transfer
tion

DQ0 D0

D7 CRC0 1

DQ1 D8

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MT40A1G8SA-075:H Datasheet file may be downloaded here without warranties.

Datasheet ID: MT40A1G8SA-075:H 648385