RC28F256J3C125SL7HE

RC28F256J3C125SL7HE Datasheet

64-Ball Easy BGA RC28F320J3A-110 RC28F640J3A-120 RC28F128J3A-150 RC28F320J3C-110 RC28F640J3C-115 RC28F640J3C-120 RC28F128J3C-120 RC28F128J3C-150 RC28F256J3C-125 64-Ball Pb-Free Easy BGA PC28F256J3C125 PC28F128J3C120 PC28F640J3C115 PC28F320J3C110

Part	Datasheet
RC28F256J3C125SL7HE	RC28F256J3C125SL7HE (pdf)

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Intel Memory J3 256-Mbit x8/x16 Product Features Datasheet • Performance • Architecture 110/115/120/150 ns Initial Access Speed Multi-Level Cell Technology High 125 ns Initial Access Speed 256 Mbit density only 25 ns Asynchronous Page mode Reads 30 ns Asynchronous Page mode Reads 256Mbit density only 32-Byte Write Buffer µs per byte effective programming time • Software Density at Low Cost High-Density Symmetrical 128-Kbyte Blocks Mbit 256 Blocks 0.18µm only Mbit 128 Blocks Mbit 64 Blocks Mbit 32 Blocks • Quality and Reliability Operating Temperature -40 °C to +85 °C Program and Erase suspend support 100K Minimum Erase Cycles per Block Flash Data Integrator FDI , Common Flash Interface CFI Compatible • Security 128-bit Protection Register Unique Device Identifier User Programmable OTP Cells Absolute Protection with VPEN = GND Individual Block Locking Block Erase/Program Lockout during Power Transitions µm ETOX VII Process J3C µm ETOX VI Process J3A • Packaging and Voltage 56-Lead TSOP Package 64-Ball Easy BGA Package Lead-free packages available 48-Ball VF BGA Package 32 and 64 Mbit x16 only VCC = V to V VCCQ = V to V Capitalizing on Intel’s and micron, two-bit-per-cell technology, the Intel Memory J3 device provides 2X the bits in 1X the space, with new features for mainstream performance. Offered in 256Mbit 32-Mbyte , 128-Mbit 16-Mbyte , 64-Mbit, and 32-Mbit densities, the J3 device brings reliable, two-bitper-cell storage technology to the flash market segment. Benefits include more density in less space, high-speed interface, lowest cost-per-bit NOR device, support for code and data storage, and easy migration to future devices. Using the same NOR-based ETOX technology as Intel’s one-bit-per-cell products, the J3 device takes advantage of over one billion units of flash manufacturing experience since As a result, J3 components are ideal for code and data applications where high density and low cost are required. Examples include networking, telecommunications, digital set top boxes, audio recording, and digital imaging. By applying FlashFile memory family pinouts, J3 memory components allow easy design migrations from existing Word-Wide FlashFile memory 28F160S3 and 28F320S3 , and first generation Intel memory 28F640J5 and 28F320J5 devices. J3 memory components deliver a new generation of forward-compatible software support. By using the Common Flash Interface CFI and the Scalable Command Set SCS , customers can take advantage of density upgrades and optimized write capabilities of future Intel memory devices. Manufactured on micron ETOX VII J3C and micron ETOX VI J3A process technology, the J3 memory device provides the highest levels of quality and reliability. Notice This document contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Order Number 290667-021 March 2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 3 Volt Intel Memory may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at Copyright 2005, Intel Corporation. All rights reserved. Intel and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Datasheet Contents Contents Nomenclature Functional Overview Block Diagram Memory Map Package Information 56-Lead TSOP Package Easy BGA J3 Package VF-BGA J3 Package Ballout and Signal Descriptions Easy BGA Ballout 32/64/128/256 Mbit 56-Lead TSOP 32/64/128/256 VF BGA Ballout 32 and 64 Mbit Signal Descriptions Maximum Ratings and Operating Absolute Maximum Ratings Operating Conditions Electrical Specifications DC Current Characteristics DC Voltage AC Characteristics Read Write Operations Block Erase, Program, and Lock-Bit Configuration Performance Reset AC Test Capacitance Power and Reset Specifications Power-Up/Down Power Supply Reset Bus Operations Bus Operations Overview Bus Read Operation Bus Write Operation Output Disable Reset/Power-Down Datasheet Contents Device Commands 35 Read 37 Read 37 Asynchronous Page Mode Read 37 Enhanced Configuration Register 38 Read Identifier Codes 39 Read Status 39 Read 41 Programming Operations 42 Byte/Word Program 42 Write to 42 Program 43 Program 43 Erase 44 Block 44 Block Erase Suspend 44 Erase Resume 45 Security Modes 46 Set Block 46 Clear Block 46 Protection Register Program 47 Reading the Protection 47 Programming the Protection 47 Locking the Protection 47 Array Protection 49 Special 50 Set Read Configuration Register Command 50 Status STS 50 Appendix A Common Flash Appendix B Flow Charts Appendix C Design Considerations Appendix D Additional Information Appendix E Ordering Datasheet Contents 03/16/00 06/26/00 2/15/01 04/13/01 Version -001 -002 -003 -004 -005 -006 -007 -008 Original Version indicated on block diagram Changed Minimum Block Erase time,IOL, IOH, Page Mode and Byte Mode currents. Modified RP# on AC Waveform for Write Operations Changed Block Erase time and tAVWH Removed all references to 5 V I/O operation Corrected Ordering Information, Valid Combinations entries Changed Min program time to 211 µs Added DU to Lead Descriptions table Changed Chip Scale Package to Ball Grid Array Package Changed default read mode to page mode Removed erase queuing from Figure 10, Block Erase Flowchart Added Program Max time Added Erase Max time Added Max page mode read current Moved tables to correspond with sections Fixed typographical errors in ordering information and DC parameter table Removed VCCQ1 setting and changed VCCQ2/3 to VCCQ1/2 Added recommended resister value for STS pin Change operation temperature range Removed note that rp# could go to 14 V Removed VOL of V Removed VOH of V Updated ICCR Typ values Added Max lock-bit program and lock times Added note on max measurements Updated cover sheet statement of 700 million units to one billion Corrected Table 10 to show correct maximum program times Corrected error in Max block program time in section Corrected typical erase time in section Updated cover page to reflect 100K minimum erase cycles Updated cover page to reflect 110 ns 32M read speed Removed Set Read Configuration command from Table 4 Updated Table 8 to reflect reserved bits are 1-7 not 2-7 Updated Table 16 bit 2 definition from R to PSS Changed VPENLK Max voltage from V to V, Section DC Characteristics Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Section AC Operations 1,2 Updated write parameter W13 tWHRL from 90 ns to 500 ns, Section AC Operations Updated Max. Program Suspend Latency W16 tWHRH1 from 30 to 75 µs, Section Block Erase, Program, and Lock-Bit Configuration Performance 1,2,3 Datasheet Contents 10/31/01 03/21/02 Version -009 -010 -011 Added Figure 4, 3 Volt Intel Memory VF BGA Package 32 Mbit Added Figure 5, 3 Volt Intel Memory VF BGA Mechanical Specifications Updated Operating Temperature Range to Extended Section and Table 22 Reduced tEHQZ to 35 ns. Reduced tWHEH to 0 ns Added parameter values for °C operation to Lock-Bit and Suspend Latency Updated VLKO and VPENLK to V Removed Note #4, Section and Section Minor text edits Added notes under lead descriptions for VF BGA Package Removed V - V Vcc, and Vccq columns under AC Characteristics Removed byte mode read current row un DC characteristics Added ordering information for VF BGA Package Minor text edits Changed datasheet to reflect the best known methods Updated max value for Clear Block Lock-Bits time Minor text edits 12/12/02 01/24/03 12/09/03 1/3/04 1/23/04 1/23/04 5/19/04 7/7/04 11/23/04 3/24/05 -012 -013 -014 -015 -016 -016 -018 -019 -020 -021 Added nomenclature for J3C µm devices. Added 115 ns access speed 64 Mb J3C device. Added 120 ns access speed 128 Mb J3C device. Added “TE” package designator for J3C TSOP package. Added 256Mbit device timings, device ID, and CFI information. Also corrected VLKO specification. Corrected memory block count from 257 to Memory block count fix. Restructured the datasheet layout. Added lead-free part numbers and 8-word page information. Added Note to DC Voltage Characteristics table “Speed Bin” to Read Operations table Corrected format for AC Waveform for Reset Operation figure Corrected “R” and “8W” headings in Enhanced Configuration Register table because they were transposed Added 802 and 803 to ordering information and corrected 56Lead TSOP combination number. Corrected ordering information. Datasheet 256-Mbit J3 x8/x16 Introduction This document describes the Intel Memory J3 device. It includes a description of device features, operations, and specifications. Nomenclature AMIN: AMAX: Block Clear CUI MLC OTP PLR PR PRD Program RFU Set SR SRD VPEN WSM ECR XSR: AMIN = A0 for x8 AMIN = A1 for x16 32 Mbit AMAX = A21 64 Mbit AMAX = A22 128 Mbit AMAX = A23 256 Mbit AMAX = A24 A group of flash cells that share common erase circuitry and erase simultaneously Indicates a logic zero 0 Command User Interface Multi-Level Cell One Time Programmable Protection Lock Register Protection Register Protection Register Data To write data to the flash array Reserved for Future Use Indicates a logic one 1 Status Register Status Register Data Refers to a signal or package connection name Refers to timing or voltage levels Write State Machine Extended Configuration Register eXtended Status Register Conventions 0x 0b k noun M noun Nibble Byte Word Kword Kb Mb Brackets: Hexadecimal prefix Binary prefix 1,000 1,000,000 4 bits 8 bits 16 bits 1,024 words 1,024 bits 1,024 bytes 1,048,576 bits 1,048,576 bytes Square brackets [] will be used to designate group membership or to define a group of signals with similar function i.e., A[21:1], SR[4,1] and D[15:0] . Datasheet 256-Mbit J3 x8/x16 Functional Overview The Intel memory family contains high-density memories organized as 32 Mbytes or 16Mwords 256-Mbit, available on the 0.18µm lithography process only , 16 Mbytes or 8 Mwords 128-Mbit , 8 Mbytes or 4 Mwords 64-Mbit , and 4 Mbytes or 2 Mwords 32-Mbit . These devices can be accessed as 8- or 16-bit words. The 128-Mbit device is organized as one-hundredtwenty-eight 128-Kbyte 131,072 bytes erase blocks. The 64-Mbit device is organized as sixtyfour 128-Kbyte erase blocks while the 32-Mbit device contains thirty-two 128-Kbyte erase blocks. A 128-bit Protection Register has multiple uses, including unique flash device identification. The device’s optimized architecture and interface dramatically increases read performance by supporting page-mode reads. This read mode is ideal for non-clock memory systems. A Common Flash Interface CFI permits software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backwardcompatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. Scalable Command Set SCS allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging e.g., memory card, SIMM, or direct-to-board placement . Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. A Command User Interface CUI serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine WSM automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. A block erase operation erases one of the device’s 128-Kbyte blocks typically within one independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or program data from any other block. Similarly, program suspend allows system software to suspend programming byte/ word program and write-to-buffer operations to read data or execute code from any other block that is not being suspended. Each device incorporates a Write Buffer of 32 bytes 16 words to allow optimum programming performance. By using the Write Buffer, data is programmed in buffer increments. This feature can improve system program performance more than 20 times over non-Write Buffer writes. Blocks are selectively and individually lockable in-system.Individual block locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program operations. Lock-bit configuration operations set and clear lock-bits Set Block Lock-Bit and Clear Block Lock-Bits commands . The Status Register indicates when the WSM’s block erase, program, or lock-bit configuration operation is finished. The STS STATUS output gives an additional indicator of WSM activity by providing both a hardware signal of status versus software polling and status masking interrupt masking for background block erase, for example . Status indication using STS minimizes both CPU overhead and system power consumption. When configured in level mode default mode , it acts as a RY/ BY# signal. When low, STS indicates that the WSM is performing a block erase, program, or lockbit configuration. STS-high indicates that the WSM is ready for a new command, block erase is Datasheet 256-Mbit J3 x8/x16 suspended and programming is inactive , program is suspended, or the device is in reset/powerdown mode. Additionally, the configuration command allows the STS signal to be configured to pulse on completion of programming and/or block erases. Three CE signals are used to enable and disable the device. A unique CE logic design see Table 13, “Chip Enable Truth Table” on page 33 reduces decoder logic typically required for multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4chip miniature card or SIMM module. The BYTE# signal allows either x8 or x16 read/writes to the device. BYTE#-low selects 8-bit mode address A0 selects between the low byte and high byte. BYTE#-high enables 16-bit operation address A1 becomes the lowest order address and address A0 is not used don’t care . A device block diagram is shown in Figure 4 on page When the device is disabled see Table 13 on page 33 , with CEx at VIH and RP# at VIH, the standby mode is enabled. When RP# is at VIL, a further power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time tPHQV is required from RP# going high until data outputs are valid. Likewise, the device has a wake time tPHWL from RP#-high until writes to the CUI are recognized. With RP# at VIL, the WSM is reset and the Status Register is cleared. Block Diagram Figure 3 Volt Intel Memory Block Diagram D[15:0] VCCQ A[2:0] A[MAX:MIN] Input Buffer Address Latch Address Counter Appendix E Ordering Information 256-Mbit J3 x8/x16 PC2 8 F 2 5 6 J 3 C- 1 2 5 Package E = 56-Lead TSOP J3A, 802 TE= 56-Lead TSOP J3C, 803 JS = Pb-Free 56-TSOP RC = 64-Ball Easy BGA GE = 48-Ball VFBGA PC = 64-Ball Pb-Free Easy BGA Product line designator for all Flash products Device Density 256 = x8/x16 256 Mbit 128 = x8/x16 128 Mbit 640 = x8/x16 64 Mbit 320 = x8/x16 32 Mbit Access Speed ns 1 256 Mbit = 125 128 Mbit = 150, 120 64 Mbit = 120, 115 32 Mbit = 110 A = micron lithography C = micron lithography Voltage VCC/VPEN 3 = 3 V/3 V Product Family J = Intel memory, 2 bits-per-cell NOTE Speeds are for either the standard asynchronous read access times or for the first access of a page-mode read sequence. VALID COMBINATIONS 56-Lead TSOP E28F320J3A-110 E28F640J3A-120 E28F128J3A-150 TE28F320J3C-110 TE28F640J3C-115 TE28F640J3C-120 TE28F128J3C-120 TE28F128J3C-150 TE28F256J3C-125 56-Lead Pb-Free TSOP JS28F256J3C125 JS28F128J3C120 JS28F640J3C115 JS28F320J3C110 64-Ball Easy BGA RC28F320J3A-110 RC28F640J3A-120 RC28F128J3A-150 RC28F320J3C-110 RC28F640J3C-115 RC28F640J3C-120 RC28F128J3C-120 RC28F128J3C-150 RC28F256J3C-125 64-Ball Pb-Free Easy BGA PC28F256J3C125 PC28F128J3C120 PC28F640J3C115 PC28F320J3C110 48-Ball VF BGA GE28F320J3A-110 GE28F320J3C-110 GE28F640J3C-115 GE28F640J3C-120 Datasheet 256-Mbit J3 x8/x16 Datasheet

PDF Datasheet Preview

Intel Memory J3
256-Mbit x8/x16

Product Features

Datasheet
• Performance
• Architecture
110/115/120/150 ns Initial Access Speed Multi-Level Cell Technology High
125 ns Initial Access Speed 256 Mbit density only
25 ns Asynchronous Page mode Reads
30 ns Asynchronous Page mode Reads 256Mbit density only
32-Byte Write Buffer µs per byte effective programming time
• Software

Density at Low Cost

High-Density Symmetrical 128-Kbyte Blocks Mbit 256 Blocks 0.18µm only Mbit 128 Blocks Mbit 64 Blocks Mbit 32 Blocks
• Quality and Reliability Operating Temperature -40 °C to +85 °C

Program and Erase suspend support
100K Minimum Erase Cycles per Block

Flash Data Integrator FDI , Common Flash Interface CFI Compatible
• Security
128-bit Protection Register Unique Device Identifier User Programmable OTP Cells

Absolute Protection with VPEN = GND Individual Block Locking Block Erase/Program Lockout during

Power Transitions
µm ETOX VII Process J3C
µm ETOX VI Process J3A
• Packaging and Voltage
56-Lead TSOP Package 64-Ball Easy BGA Package Lead-free packages available 48-Ball VF BGA Package 32 and
64 Mbit x16 only VCC = V to V VCCQ = V to V

Capitalizing on Intel’s and micron, two-bit-per-cell technology, the Intel Memory J3 device provides 2X the bits in 1X the space, with new features for mainstream performance. Offered in 256Mbit 32-Mbyte , 128-Mbit 16-Mbyte , 64-Mbit, and 32-Mbit densities, the J3 device brings reliable, two-bitper-cell storage technology to the flash market segment. Benefits include more density in less space, high-speed interface, lowest cost-per-bit NOR device, support for code and data storage, and easy migration to future devices.

Using the same NOR-based ETOX technology as Intel’s one-bit-per-cell products, the J3 device takes advantage of over one billion units of flash manufacturing experience since As a result, J3 components are ideal for code and data applications where high density and low cost are required. Examples include networking, telecommunications, digital set top boxes, audio recording, and digital imaging.

By applying FlashFile memory family pinouts, J3 memory components allow easy design migrations from existing Word-Wide FlashFile memory 28F160S3 and 28F320S3 , and first generation Intel memory 28F640J5 and 28F320J5 devices.

J3 memory components deliver a new generation of forward-compatible software support. By using the Common Flash Interface CFI and the Scalable Command Set SCS , customers can take advantage of density upgrades and optimized write capabilities of future Intel memory devices. Manufactured on micron ETOX VII J3C and micron ETOX VI J3A process technology, the J3 memory device provides the highest levels of quality and reliability.

Notice This document contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.

Order Number 290667-021 March 2005

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 3 Volt Intel Memory may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at

Copyright 2005, Intel Corporation. All rights reserved.

Intel and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.

Datasheet

Contents

Contents

Nomenclature

Functional Overview Block Diagram Memory Map

Package Information 56-Lead TSOP Package Easy BGA J3 Package VF-BGA J3 Package

Ballout and Signal Descriptions Easy BGA Ballout 32/64/128/256 Mbit 56-Lead TSOP 32/64/128/256 VF BGA Ballout 32 and 64 Mbit Signal Descriptions

Maximum Ratings and Operating Absolute Maximum Ratings Operating Conditions

Electrical Specifications DC Current Characteristics DC Voltage

AC Characteristics Read Write Operations Block Erase, Program, and Lock-Bit Configuration Performance Reset AC Test Capacitance

Power and Reset Specifications Power-Up/Down Power Supply Reset

Bus Operations Bus Operations Overview Bus Read Operation Bus Write Operation Output Disable Reset/Power-Down

Datasheet

Contents

Device Commands 35

Read 37 Read 37 Asynchronous Page Mode Read 37 Enhanced Configuration Register 38 Read Identifier Codes 39 Read Status 39 Read 41

Programming Operations 42 Byte/Word Program 42 Write to 42 Program 43 Program 43

Erase 44 Block 44 Block Erase Suspend 44 Erase Resume 45

Security Modes 46 Set Block 46 Clear Block 46 Protection Register Program 47 Reading the Protection 47 Programming the Protection 47 Locking the Protection 47 Array Protection 49

Special 50 Set Read Configuration Register Command 50 Status STS 50

Appendix A Common Flash

Appendix B Flow Charts

Appendix C Design Considerations

Appendix D Additional Information
Appendix E Ordering

Datasheet

Contents
03/16/00
06/26/00
2/15/01
04/13/01

Version
-001 -002 -003 -004
-005
-006
-007 -008

Original Version
indicated on block diagram Changed Minimum Block Erase time,IOL, IOH, Page Mode and Byte Mode currents. Modified RP# on AC Waveform for Write Operations
Changed Block Erase time and tAVWH Removed all references to 5 V I/O operation Corrected Ordering Information, Valid Combinations entries Changed Min program time to 211 µs Added DU to Lead Descriptions table Changed Chip Scale Package to Ball Grid Array Package Changed default read mode to page mode Removed erase queuing from Figure 10, Block Erase Flowchart
Added Program Max time Added Erase Max time Added Max page mode read current Moved tables to correspond with sections Fixed typographical errors in ordering information and DC parameter table Removed VCCQ1 setting and changed VCCQ2/3 to VCCQ1/2 Added recommended resister value for STS pin Change operation temperature range Removed note that rp# could go to 14 V Removed VOL of V Removed VOH of V Updated ICCR Typ values Added Max lock-bit program and lock times Added note on max measurements

Updated cover sheet statement of 700 million units to one billion Corrected Table 10 to show correct maximum program times Corrected error in Max block program time in section Corrected typical erase time in section

Updated cover page to reflect 100K minimum erase cycles Updated cover page to reflect 110 ns 32M read speed Removed Set Read Configuration command from Table 4 Updated Table 8 to reflect reserved bits are 1-7 not 2-7 Updated Table 16 bit 2 definition from R to PSS Changed VPENLK Max voltage from V to V, Section DC Characteristics Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Section AC Operations 1,2 Updated write parameter W13 tWHRL from 90 ns to 500 ns, Section AC Operations Updated Max. Program Suspend Latency W16 tWHRH1 from 30 to 75 µs, Section Block Erase, Program, and Lock-Bit Configuration Performance
1,2,3
Datasheet

Contents
10/31/01 03/21/02

Version -009 -010 -011

Added Figure 4, 3 Volt Intel Memory VF BGA Package 32 Mbit Added Figure 5, 3 Volt Intel Memory VF BGA Mechanical Specifications Updated Operating Temperature Range to Extended Section and Table 22 Reduced tEHQZ to 35 ns. Reduced tWHEH to 0 ns Added parameter values for °C operation to Lock-Bit and Suspend Latency Updated VLKO and VPENLK to V Removed Note #4, Section and Section Minor text edits
Added notes under lead descriptions for VF BGA Package Removed V - V Vcc, and Vccq columns under AC Characteristics Removed byte mode read current row un DC characteristics Added ordering information for VF BGA Package Minor text edits

Changed datasheet to reflect the best known methods Updated max value for Clear Block Lock-Bits time Minor text edits
12/12/02 01/24/03 12/09/03
1/3/04 1/23/04 1/23/04 5/19/04 7/7/04
11/23/04
3/24/05
-012 -013 -014 -015 -016 -016 -018 -019
-020
-021

Added nomenclature for J3C µm devices.

Added 115 ns access speed 64 Mb J3C device. Added 120 ns access speed 128 Mb J3C device. Added “TE” package designator for J3C TSOP package.

Added 256Mbit device timings, device ID, and CFI information. Also corrected VLKO specification.

Corrected memory block count from 257 to

Memory block count fix.

Restructured the datasheet layout.

Added lead-free part numbers and 8-word page information.
Added Note to DC Voltage Characteristics table “Speed Bin” to Read Operations table Corrected format for AC Waveform for Reset Operation figure Corrected “R” and “8W” headings in Enhanced Configuration Register table because they were transposed Added 802 and 803 to ordering information and corrected 56Lead TSOP combination number.
Corrected ordering information.

Datasheet
256-Mbit J3 x8/x16

Introduction

This document describes the Intel Memory J3 device. It includes a description of device features, operations, and specifications.

Nomenclature

AMIN:

AMAX:

Block Clear CUI MLC OTP PLR PR PRD Program RFU Set SR SRD VPEN WSM ECR XSR:

AMIN = A0 for x8 AMIN = A1 for x16 32 Mbit AMAX = A21 64 Mbit AMAX = A22 128 Mbit AMAX = A23 256 Mbit AMAX = A24 A group of flash cells that share common erase circuitry and erase simultaneously Indicates a logic zero 0 Command User Interface Multi-Level Cell One Time Programmable Protection Lock Register Protection Register Protection Register Data To write data to the flash array Reserved for Future Use Indicates a logic one 1 Status Register Status Register Data Refers to a signal or package connection name Refers to timing or voltage levels Write State Machine Extended Configuration Register eXtended Status Register

Conventions
0x 0b k noun M noun Nibble Byte Word Kword Kb Mb Brackets:

Hexadecimal prefix Binary prefix 1,000 1,000,000 4 bits 8 bits 16 bits 1,024 words 1,024 bits 1,024 bytes 1,048,576 bits 1,048,576 bytes Square brackets [] will be used to designate group membership or to define a group of signals with similar function i.e., A[21:1], SR[4,1] and D[15:0] .

Datasheet
256-Mbit J3 x8/x16

Functional Overview

The Intel memory family contains high-density memories organized as 32 Mbytes or 16Mwords 256-Mbit, available on the 0.18µm lithography process only , 16 Mbytes or 8 Mwords 128-Mbit , 8 Mbytes or 4 Mwords 64-Mbit , and 4 Mbytes or 2 Mwords 32-Mbit . These devices can be accessed as 8- or 16-bit words. The 128-Mbit device is organized as one-hundredtwenty-eight 128-Kbyte 131,072 bytes erase blocks. The 64-Mbit device is organized as sixtyfour 128-Kbyte erase blocks while the 32-Mbit device contains thirty-two 128-Kbyte erase blocks. A 128-bit Protection Register has multiple uses, including unique flash device identification.

The device’s optimized architecture and interface dramatically increases read performance by supporting page-mode reads. This read mode is ideal for non-clock memory systems.

A Common Flash Interface CFI permits software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backwardcompatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility.

Scalable Command Set SCS allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging e.g., memory card, SIMM, or direct-to-board placement . Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs.

A Command User Interface CUI serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine WSM automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations.

A block erase operation erases one of the device’s 128-Kbyte blocks typically within one independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or program data from any other block. Similarly, program suspend allows system software to suspend programming byte/ word program and write-to-buffer operations to read data or execute code from any other block that is not being suspended.

Each device incorporates a Write Buffer of 32 bytes 16 words to allow optimum programming performance. By using the Write Buffer, data is programmed in buffer increments. This feature can improve system program performance more than 20 times over non-Write Buffer writes.

Blocks are selectively and individually lockable in-system.Individual block locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program operations. Lock-bit configuration operations set and clear lock-bits Set Block Lock-Bit and Clear Block Lock-Bits commands .

The Status Register indicates when the WSM’s block erase, program, or lock-bit configuration operation is finished.

The STS STATUS output gives an additional indicator of WSM activity by providing both a hardware signal of status versus software polling and status masking interrupt masking for background block erase, for example . Status indication using STS minimizes both CPU overhead and system power consumption. When configured in level mode default mode , it acts as a RY/ BY# signal. When low, STS indicates that the WSM is performing a block erase, program, or lockbit configuration. STS-high indicates that the WSM is ready for a new command, block erase is

Datasheet
256-Mbit J3 x8/x16
suspended and programming is inactive , program is suspended, or the device is in reset/powerdown mode. Additionally, the configuration command allows the STS signal to be configured to pulse on completion of programming and/or block erases.

Three CE signals are used to enable and disable the device. A unique CE logic design see Table 13, “Chip Enable Truth Table” on page 33 reduces decoder logic typically required for multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4chip miniature card or SIMM module.

The BYTE# signal allows either x8 or x16 read/writes to the device. BYTE#-low selects 8-bit mode address A0 selects between the low byte and high byte. BYTE#-high enables 16-bit operation address A1 becomes the lowest order address and address A0 is not used don’t care . A device block diagram is shown in Figure 4 on page

When the device is disabled see Table 13 on page 33 , with CEx at VIH and RP# at VIH, the standby mode is enabled. When RP# is at VIL, a further power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time tPHQV is required from RP# going high until data outputs are valid. Likewise, the device has a wake time tPHWL from RP#-high until writes to the CUI are recognized. With RP# at VIL, the WSM is reset and the Status Register is cleared.

Block Diagram

Figure 3 Volt Intel Memory Block Diagram

D[15:0]

VCCQ

A[2:0]

A[MAX:MIN]

Input Buffer

Address Latch

Address Counter
Appendix E Ordering Information
256-Mbit J3 x8/x16

PC2 8 F 2 5 6 J 3 C- 1 2 5

Package E = 56-Lead TSOP J3A, 802 TE= 56-Lead TSOP J3C, 803 JS = Pb-Free 56-TSOP RC = 64-Ball Easy BGA GE = 48-Ball VFBGA PC = 64-Ball Pb-Free Easy BGA

Product line designator for all Flash products

Device Density 256 = x8/x16 256 Mbit 128 = x8/x16 128 Mbit 640 = x8/x16 64 Mbit 320 = x8/x16 32 Mbit

Access Speed ns 1 256 Mbit = 125 128 Mbit = 150, 120 64 Mbit = 120, 115 32 Mbit = 110

A = micron lithography C = micron lithography

Voltage VCC/VPEN 3 = 3 V/3 V

Product Family J = Intel memory,
2 bits-per-cell

NOTE Speeds are for either the standard asynchronous read access times or for the first access of a page-mode read sequence.

VALID COMBINATIONS
56-Lead TSOP E28F320J3A-110 E28F640J3A-120 E28F128J3A-150 TE28F320J3C-110 TE28F640J3C-115 TE28F640J3C-120 TE28F128J3C-120 TE28F128J3C-150 TE28F256J3C-125 56-Lead Pb-Free TSOP JS28F256J3C125 JS28F128J3C120 JS28F640J3C115 JS28F320J3C110
64-Ball Easy BGA RC28F320J3A-110 RC28F640J3A-120 RC28F128J3A-150 RC28F320J3C-110 RC28F640J3C-115 RC28F640J3C-120 RC28F128J3C-120 RC28F128J3C-150 RC28F256J3C-125 64-Ball Pb-Free Easy BGA PC28F256J3C125 PC28F128J3C120 PC28F640J3C115 PC28F320J3C110
48-Ball VF BGA GE28F320J3A-110 GE28F320J3C-110 GE28F640J3C-115 GE28F640J3C-120

Datasheet
256-Mbit J3 x8/x16

Datasheet

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Datasheet ID: RC28F256J3C125SL7HE 638917