IDT5V9950PFGI8

IDT5V9950PFGI8 Datasheet

IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.

Part	Datasheet
IDT5V9950PFGI8	IDT5V9950PFGI8 (pdf)

Related Parts	Information
IDT5V9950PFGI	IDT5V9950PFGI
IDT5V9950PFI	IDT5V9950PFI

PDF Datasheet Preview
IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. INDUSTRIAL TEMPERATURE RANGE IDT5V9950 FEATURES: • Ref input is 5V tolerant • 4 pairs of programmable skew outputs • Low skew 185ps same pair, 250ps all outputs • Selectable positive or negative edge synchronization: Excellent for DSP applications • Synchronous output enable • Input frequency 6MHz to 200MHz • Output frequency 6MHz to 200MHz • 2x, 4x, 1/2, and 1/4 outputs • 3-level inputs for skew and PLL range control • PLL bypass for DC testing • External feedback, internal loop filter • 12mA balanced drive outputs • Low Jitter <100ps cycle-to-cycle • Available in TQFP package DESCRIPTION: The IDT5V9950 is a high fanout 3.3V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5V9950 has eight programmable skew outputs in four banks of Skew is controlled by 3-level input signals that may be hard-wired to appropriate HIGH-MID-LOW levels. When the sOE pin is held low, all the outputs are synchronously enabled. However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are synchronously disabled. Furthermore, when PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF. The IDT5V9950 has LVTTL outputs with 12mA balanced drive outputs. FUNCTIONAL BLOCK DIAGRAM REF FB PE TEST 3 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE c 2002 Integrated Device Technology, Inc. Skew Select 1F1:0 Skew Select 2F1:0 Skew Select 3F1:0 Skew Select 4F1:0 1Q0 1Q1 2Q0 2Q1 3Q0 3Q1 4Q0 4Q1 OCTOBER 2008 DSC 5870/6 IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. INDUSTRIAL TEMPERATURE RANGE GND 3Q1 3Q0 VDDQ FB VDDQ 2Q1 2Q0 PIN CONFIGURATION 3F0 FS VDD REF GND TEST 2F1 2F0 3F1 4F0 4F1 PE VDDQ 4Q1 4Q0 GND 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1F1 1F0 sOE VDDQ 1Q0 1Q1 GND ORDERING INFORMATION Device Type Package INDUSTRIAL TEMPERATURE RANGE -40°C to +85°C Industrial PF PFG Thin Quad Flat Pack TQFP - Green 5V9950 3.3V Programmable Skew PLL Clock Driver TurboClock II Jr. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support:

PDF Datasheet Preview

IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.

INDUSTRIAL TEMPERATURE RANGE

IDT5V9950

FEATURES:
• Ref input is 5V tolerant
• 4 pairs of programmable skew outputs
• Low skew 185ps same pair, 250ps all outputs
• Selectable positive or negative edge synchronization:

Excellent for DSP applications
• Synchronous output enable
• Input frequency 6MHz to 200MHz
• Output frequency 6MHz to 200MHz
• 2x, 4x, 1/2, and 1/4 outputs
• 3-level inputs for skew and PLL range control
• PLL bypass for DC testing
• External feedback, internal loop filter
• 12mA balanced drive outputs
• Low Jitter <100ps cycle-to-cycle
• Available in TQFP package

DESCRIPTION:

The IDT5V9950 is a high fanout 3.3V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5V9950 has eight programmable skew outputs in four banks of Skew is controlled by 3-level input signals that may be hard-wired to appropriate HIGH-MID-LOW levels.

When the sOE pin is held low, all the outputs are synchronously enabled. However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are synchronously disabled.

Furthermore, when PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF. The IDT5V9950 has LVTTL outputs with 12mA balanced drive outputs.

FUNCTIONAL BLOCK DIAGRAM

REF FB

PE TEST 3

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE
c 2002 Integrated Device Technology, Inc.

Skew Select
1F1:0

Skew Select
2F1:0

Skew Select
3F1:0

Skew Select
4F1:0
1Q0 1Q1
2Q0 2Q1
3Q0 3Q1
4Q0 4Q1

OCTOBER 2008

DSC 5870/6

IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.

INDUSTRIAL TEMPERATURE RANGE

GND 3Q1 3Q0 VDDQ

FB VDDQ 2Q1 2Q0

PIN CONFIGURATION
3F0 FS VDD REF GND TEST 2F1 2F0
3F1 4F0 4F1 PE VDDQ 4Q1 4Q0 GND
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1F1 1F0 sOE VDDQ 1Q0 1Q1 GND
ORDERING INFORMATION

Device Type Package

INDUSTRIAL TEMPERATURE RANGE
-40°C to +85°C Industrial

PF PFG

Thin Quad Flat Pack TQFP - Green
5V9950 3.3V Programmable Skew PLL Clock Driver TurboClock II Jr.

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT5V9950PFGI8 Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT5V9950PFGI8 637307