LAN9312-NU

LAN9312-NU Datasheet

LAN9312

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LAN9312-NU	LAN9312-NU (pdf)

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LAN9312-NZW	LAN9312-NZW

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LAN9312 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface PRODUCT FEATURES Highlights High performance and full featured 2 port switch with VLAN, QoS packet prioritization, Rate Limiting, IGMP monitoring and management functions Easily interfaces to most 32-bit embedded CPU’s Unique Virtual PHY feature simplifies software development by mimicking the multiple switch ports as a single port MAC/PHY Integrated IEEE 1588 Hardware Time Stamp Unit Target Applications Cable, satellite, and IP set-top boxes Digital televisions Digital video recorders VoIP/Video phone systems Home gateways Test/Measurement equipment Industrial automation systems Key Benefits Ethernet Switch Fabric 32K buffer RAM 1K entry forwarding table Port based IEEE 802.1Q VLAN support 16 groups Programmable IEEE 802.1Q tag insertion/removal IEEE 802.1d spanning tree protocol support QoS/CoS Packet prioritization 4 dynamic QoS queues per port Input priority determined by VLAN tag, DA lookup, TOS, DIFFSERV or port default value Programmable class of service map based on input priority Remapping of 802.1Q priority field on per port basis Programmable rate limiting at the ingress/egress ports with random early discard, per port / priority IGMP v1/v2/v3 monitoring for Multicast packet filtering Programmable filter by MAC address Switch Management Port mirroring/monitoring/sniffing ingress and/or egress traffic on any ports or port pairs Fully compliant statistics MIB gathering counters Control registers configurable on-the-fly Datasheet Ports 2 internal 10/100 PHYs with HP Auto-MDIX support Fully compliant with IEEE standards 10BASE-T and 100BASE-TX support Full and half duplex support Full duplex flow control Backpressure forced collision half duplex flow control Automatic flow control based on programmable levels Automatic 32-bit CRC generation and checking Automatic payload padding 2K Jumbo packet support Programmable interframe gap, flow control pause value Full transmit/receive statistics Auto-negotiation Automatic MDI/MDI-X Loop-back mode High-performance host bus interface Provides in-band network communication path Access to management registers Simple, SRAM-like interface 32-bit data bus Big, little, and mixed endian support Large TX and RX FIFO’s for high latency applications Programmable water marks and threshold levels Host interrupt support IEEE 1588 Hardware Time Stamp Unit Global 64-bit tunable clock Master or slave mode per port Time stamp on TX or RX of Sync and Delay_req packets per port, Timestamp on GPIO 64-bit timer comparator event generation GPIO or IRQ Comprehensive Power Management Features Wake on LAN Wake on link status change energy detect Magic packet wakeup indicator event signal Other Features General Purpose Timer Serial EEPROM interface I2C master or MicrowireTM master for non-managed configuration Programmable GPIOs/LEDs Single 3.3V power supply Available in Commercial Temp. Range SMSC LAN9312 DATASHEET High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Order Numbers LAN9312-NU For 128-Pin, VTQFP Lead-Free RoHS Compliant Package 0 TO 70°C Temp Range LAN9312-NZW For 128-Pin, XVTQFP Lead-Free RoHS Compliant Package 0 TO 70°C Temp Range LAN9312-NU-TR For 128-Pin, VTQFP Lead-Free RoHS Compliant Package 0 TO 70°C Temp Range LAN9312-NZW-TR For 128-Pin, XVTQFP Lead-Free RoHS Compliant Package 0 TO 70°C Temp Range TR indicates tape & reel option. This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit Figure Internal LAN9312 Block Diagram. 21 Figure System Block Diagram. 25 Figure LAN9312 128-VTQFP Pin Assignments TOP VIEW 26 Figure LAN9312 128-XVTQFP Pin Assignments TOP VIEW . 27 Figure PME and PME_INT Signal Generation 47 Figure Functional Interrupt Register Hierarchy 50 Figure Switch Fabric CSR Write Access Flow Diagram 57 Figure Switch Fabric CSR Read Access Flow Diagram 58 Figure ALR Table Entry Structure 63 Figure Switch Engine Transmit Queue Selection 67 Figure Switch Engine Transmit Queue Calculation. 68 Figure VLAN Table Entry Structure. 70 Figure Switch Engine Ingress Flow Priority Selection 73 Figure Switch Engine Ingress Flow Priority Calculation 73 Figure Hybrid Port Tagging and Un-tagging 80 Figure Port x PHY Block Diagram 83 Figure 100BASE-TX Transmit Data Path 84 Figure 100BASE-TX Receive Data Path. 87 Figure Direct Cable Connection vs. Cross-Over Cable Connection 93 Figure Little Endian Byte Ordering 100 Figure Big Endian Byte Ordering. 100 Figure Functional Timing for PIO Read Operation 106 Figure Functional Timing for PIO Burst Read Operation. 107 Figure Functional Timing for RX Data FIFO Direct PIO Read Operation 108 Figure Functional Timing for RX Data FIFO Direct PIO Burst Read Operation 109 Figure Functional Timing for PIO Write Operation 110 Figure Functional Timing for TX Data FIFO Direct PIO Write Operation 111 Figure VLAN Frame 114 Figure Example EEPROM MAC Address Setup 120 Figure Simplified Host TX Flow Diagram 123 Figure TX Buffer Format 124 Figure TX Example 129 Figure TX Example 130 Figure Host Receive Routine Using Interrupts 133 Figure Host Receive Routine Using Polling 133 Figure RX Packet Format 135 Figure EEPROM Access Flow Diagram 139 Figure I2C Cycle 141 Figure I2C EEPROM Addressing 141 Figure I2C EEPROM Byte Read 142 Figure I2C EEPROM Sequential Byte Reads 142 Figure I2C EEPROM Byte Write 143 Figure EEPROM ERASE Cycle 145 Figure EEPROM ERAL Cycle 146 Figure EEPROM EWDS Cycle 146 Figure 10.10EEPROM EWEN Cycle 147 Figure 10.11EEPROM READ Cycle 147 Figure 10.12EEPROM WRITE Cycle 148 Figure 10.13EEPROM WRAL Cycle 148 Figure 10.14EEPROM Loader Flow Diagram 150 Figure IEEE 1588 Block Diagram 155 Figure IEEE 1588 Message Time Stamp Point. 156 DATASHEET SMSC LAN9312 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Figure LAN9312 Base Register Memory Map. 166 Figure Output Equivalent Test Load 444 Figure nRST Reset Pin Timing 445 Figure Power-On Configuration Strap Latching Timing. 446 Figure PIO Read Cycle Timing 447 Figure PIO Burst Read Cycle Timing 448 Figure RX Data FIFO Direct PIO Read Cycle Timing 449 Figure RX Data FIFO Direct PIO Burst Read Cycle Timing 450 Figure PIO Write Cycle Timing 451 Figure TX Data FIFO Direct PIO Write Cycle Timing 452 Figure 15.10Microwire Timing 453 Figure 128-VTQFP Package Definition 455 Figure 128-VTQFP Recommended PCB Land Pattern. 456 Figure 128-XVTQFP Package Definition. 457 Figure 128-XVTQFP Recommended PCB Land Pattern 458 SMSC LAN9312 DATASHEET High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet List of Tables Table Buffer Types 18 Table Register Bit Types 19 Table LAN Port 1 Pins 28 Table LAN Port 2 Pins 29 Table LAN Port 1 & 2 Power and Common Pins 29 Table Host Bus Interface Pins 30 Table EEPROM Pins 31 Table Dedicated Configuration Strap Pins. 33 Table Miscellaneous Pins 34 Table PLL Pins 35 Table Core and I/O Power and Ground Pins 35 Table No-Connect Pins 35 Table Reset Sources and Affected LAN9312 Circuitry 37 Table Soft-Strap Configuration Strap Definitions. 41 Table Hard-Strap Configuration Strap Definitions 46 Table Switch Fabric Flow Control Enable Logic 59 Table Spanning Tree States 70 Table Typical Ingress Rate Settings 72 Table Typical Broadcast Rate Settings 74 Table Typical Egress Rate Settings. 78 Table Default PHY Serial MII Addressing 82 Table 4B/5B Code Table 85 Table PHY Interrupt Sources. 94 Table Read After Write Timing Rules 102 Table Read After Read Timing Rules 105 Table Address Filtering Modes 115 Table Wake-Up Frame Filter Register Structure 117 Table Filter i Byte Mask Bit Definitions 117 Table Filter i Command Bit Definitions 117 Table Filter i Offset Bit Definitions 118 Table Filter i CRC-16 Bit Definitions 118 Table EEPROM Byte Ordering and Register Correlation 119 Table TX/RX FIFO Configurable Sizes 121 Table Valid TX/RX FIFO Allocations 122 Table TX Command 'A' Format 125 Table TX Command 'B' Format 126 Table TX DATA Start Offset 126 Table I2C/Microwire Master Serial Management Pins Characteristics. 137 Table I2C EEPROM Size Ranges 140 Table Microwire EEPROM Size Ranges 144 Table Microwire Command Set for 7 Address Bits 144 Table Microwire Command Set for 9 Address Bits 144 Table Microwire Command Set for 11 Address Bits 145 Table EEPROM Contents Format Overview 149 Table EEPROM Configuration Bits 151 Table IEEE 1588 Message Type Detection. 156 Table Time Stamp Capture Delay 157 Table PTP Multicast Addresses. 158 Table Typical IEEE 1588 Clock Addend Values 159 Table LED Operation as a Function of LED_CFG[9:8] 164 Table System Control and Status Registers 168 Table Backpressure Duration Bit Mapping 190 DATASHEET SMSC LAN9312 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 DATASHEET High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Chapter 1 Preface General Terms 100BT ADC ALR BLW BM BPDU Byte CSMA/CD CSR CTR DA DWORD EPC FCS FIFO FSM GPIO HBI HBIC Host IGMP Inbound Level-Triggered Sticky Bit lsb MDI MDIX 100BASE-T 100Mbps Fast Ethernet, IEEE 802.3u Analog-to-Digital Converter Address Logic Resolution Baseline Wander Buffer Manager - Part of the switch fabric Bridge Protocol Data Unit - Messages which carry the Spanning Tree Protocol information 8-bits Carrier Sense Multiple Access / Collision Detect Control and Status Registers Counter Destination Address 32-bits EEPROM Controller Frame Check Sequence - The extra checksum characters added to the end of an Ethernet frame, used for error detection and correction. First In First Out buffer Finite State Machine General Purpose I/O Host Bus Interface. The physical bus connecting the LAN9312 to the host. Also referred to as the Host Bus. Host Bus Interface Controller. The hardware module that interfaces the LAN9312 to the HBI. External system Includes processor, application software, etc. Internet Group Management Protocol Refers to data input to the LAN9312 from the host This type of status bit is set whenever the condition that it represents is asserted. The bit remains set until the condition is no longer true, and the status bit is cleared by writing a zero. Least Significant Bit Least Significant Byte Medium Dependant Interface Media Independent Interface with Crossover DATASHEET SMSC LAN9312 MII MIIM MIL MLT-3 msb NRZI N/A NC OUI Outbound PIO cycle PISO PLL PTP RESERVED RTC SA SFD SIPO SMI SQE SSD UDP UUID WORD High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Media Independent Interface Media Independent Interface Management MAC Interface Layer Multi-Level Transmission Encoding 3-Levels . A tri-level encoding method where a change in the logic level represents a code bit “1” and the logic output remaining at the same level represents a code bit Most Significant Bit Most Significant Byte Non Return to Zero Inverted. This encoding method inverts the signal for a “1” and leaves the signal unchanged for a “0” Not Applicable No Connect Organizationally Unique Identifier Refers to data output from the LAN9312 to the host Program I/O cycle. An SRAM-like read or write cycle on the HBI. Parallel In Serial Out Phase Locked Loop Precision Time Protocol Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must always be zero for write operations. Unless otherwise noted, values are not guaranteed when reading reserved bits. Unless otherwise noted, do not read or write to reserved addresses. Real-Time Clock Source Address Start of Frame Delimiter - The 8-bit value indicating the end of the preamble of an Ethernet frame. Serial In Parallel Out Serial Management Interface Signal Quality Error also known as “heartbeat” Start of Stream Delimiter User Datagram Protocol - A connectionless protocol run on top of IP networks Universally Unique IDentifier 16-bits SMSC LAN9312 DATASHEET High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Buffer Types Table describes the pin buffer type notation used in Chapter 3, "Pin Description and Configuration," on page 26 and throughout this document. Table Buffer Types BUFFER TYPE IS O8 OD8 O12 OD12 PU AI AO AIO ICLK OCLK P Schmitt-triggered Input Output with 8mA sink and 8mA source Open-drain output with 8mA sink Output with 12mA sink and 12mA source Open-drain output with 12mA sink When a transmit queue is non-empty, it is serviced and the packet is read from the buffer RAM and sent to the transmit MAC. If there are multiple queues that require servicing, one of two methods may be used fixed priority ordering, or weighted round-robin ordering. If the Fixed Priority Queue Servicing bit in the Buffer Manager Configuration Register BM_CFG is set, a strict order, fixed priority is selected. Transmit queue 3 has the highest priority, followed by 2, 1, and If the Fixed Priority Queue Servicing bit in the Buffer Manager Configuration Register BM_CFG is cleared, a weighted roundrobin order is followed. Assuming all four queues are non-empty, the service is weighted with a 9:4:2:1 ratio queue The servicing is blended to avoid burstiness e.g. queue 3, then queue 2, then queue 3, etc. . Egress Rate Limiting Leaky Bucket For egress rate limiting, the leaky bucket algorithm is used on each output priority queue. For each output port, the bandwidth that is used by each priority queue can be limited. If any egress queue receives packets faster than the specified egress rate, packets will be accumulated in the packet memory. After the memory is used, packet dropping or flow control will be triggered. Note Egress rate limiting occurs before the Transmit Priority Queue Servicing, such that a lower priority queue will be serviced if a higher priority queue is being rate limited. The egress limiting is enabled per priority queue. After a packet is selected to be sent, its length is recorded. The switch then waits a programmable amount of time, scaled by the packet length, before servicing that queue once again. The amount of time per byte is programmed into the Buffer Manager Egress Rate registers refer to Section through Section for detailed register definitions . The value programmed is in approximately 20 nS per byte increments. Typical values are listed in Table When a port is transmitting at 10 Mbps, any setting above 39 has the effect of not limiting the rate. Table Typical Egress Rate Settings EGRESS RATE SETTING 0-3 4 5 6 7 9 12 19 39 78 158 396 794 1589 3973 7947 TIME PER BYTE 80 nS 100 nS 120 nS 140 nS 160 nS 200 nS 260 nS 400 nS 800 nS 1580 nS 3180 nS 7940 nS 15900 nS 31800 nS 79480 nS 158960 nS BANDWIDTH 64 BYTE PACKET 76 Mbps Note 66 Mbps 55 Mbps 48 Mbps 42 Mbps 34 Mbps 26 Mbps 17 Mbps 870 Kbps 440 Kbps 220 Kbps 87 Kbps 44 Kbps BANDWIDTH 512 BYTE PACKET 96 Mbps Note 78 Mbps 65 Mbps 56 Mbps 49 Mbps 39 Mbps 30 Mbps 20 Mbps 10 Mbps 5 Mbps 990 Kbps 490 Kbps 250 Kbps 98 Kbps 49 Kbps BANDWIDTH 1518 BYTE PACKET 99 Mbps Note 80 Mbps 67 Mbps 57 Mbps 50 Mbps 40 Mbps 31 Mbps 20 Mbps 10 Mbps 5 Mbps 1 Mbps 500 Kbps 250 Kbps 100 Kbps 50 Kbps DATASHEET SMSC LAN9312 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Note These are the unlimited max bandwidths when IFG and preamble are taken into account. Adding, Removing, and Changing VLAN Tags Based on the port configuration and the received packet formation, a VLAN tag can be added to, removed from, or modified in a packet. There are four received packet type cases non-tagged, prioritytagged, normal-tagged, and CPU special-tagged. There are also four possible settings for an egress port dumb, access, hybrid, and CPU. In addition, each VLAN table entry can specify the removal of the VLAN tag the entry’s un-tag bit . The tagging/un-tagging rules are specified as follows: Dumb Port - This port type generally does not change the tag. When a received packet is non-tagged, priority-tagged, or normal-tagged, the packet passes untouched. When a packet is received special-tagged from a CPU port, the special tag is removed. Access Port - This port type generally does not support tagging. When a received packet in non-tagged, the packet passes untouched. When a received packet is priority-tagged or normal-tagged, the tag is removed. When a received packet is special-tagged from a CPU port, the special tag is removed. CPU Port - Packets transmitted from this port type generally contain a special tag. Special tags are described in detail in Section "Host CPU Port Special Tagging," on page Hybrid Port - Generally, this port type supports a mix of normal-tagged and non-tagged packets. It is the most complex, but most flexible port type. For clarity, the following details the incoming un-tag instruction. As described in Section "VLAN Support," on page 70, the un-tag instruction is one of three un-tag bits from the applicable entry in the VLAN table, selected by the ingress port number. The entry in the VLAN table is either the VLAN from the received packet or the ingress ports default VID. When a received packet is non-tagged, a new VLAN tag is added if two conditions are met. First, the Insert Tag bit for the egress port in the Buffer Manager Egress Port Type Register BM_EGRSS_PORT_TYPE must be set. Second, the un-tag instruction associated with the ingress ports default VID must be cleared. The VLAN tag that is added will have a VID and Priority taken from the ingress ports default VID and priority. When a received packet is priority-tagged, either the tag is removed or it is modified. If the un-tag instruction associated with the ingress ports default VID is set, then the tag is removed. Otherwise, the tag is modified. The VID of the new VLAN tag is changed to the ingress ports default VID. If the Change Priority bit in the Buffer Manager Egress Port Type Register BM_EGRSS_PORT_TYPE for the egress port is set, then the Priority field of the new VLAN tag is also changed to the ingress ports default priority. When a received packet is normal-tagged, either the tag is removed, modified, or passed. If the un-tag instruction associated with the VID in the received packet is set, then the tag is removed. Else, if the Change Tag bit in the Buffer Manager Egress Port Type Register BM_EGRSS_PORT_TYPE for the egress port is clear, the packet is untouched. Else, if both the Change VLAN ID and the Change Priority bits in the Buffer Manager Egress Port Type Register BM_EGRSS_PORT_TYPE for the egress port are clear, the packet passes untouched. Otherwise, the tag is modified. If the Change VLAN ID bit for the egress port is set, the VOD of the new VLAN tag is changed to the egress ports default ID. If the Change Priority bit for the egress port is set, the Priority field of the new VLAN is changed to the egress ports default priority. When a packet is received special-tagged from a CPU port, the special tag is removed. SMSC LAN9312 DATASHEET High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Hybrid tagging is summarized in Figure Receive Tag Type Non-tagged Normal Tagged Priority Tagged Insert Tag Host data bus endianess control The HBI supports dynamic selection of big and little endian host byte ordering based on the END_SEL input pin. This highly flexible interface provides mixed endian access for registers and memory. Direct FIFO access modes When the FIFO_SEL input pin is high during host access, all host write operations are to the TX data FIFO and all host read operations are from the RX data FIFOs. This feature facilitates operation with host DMA controllers that do not support FIFO operations. System CSR’s The HBI allows for configuration and monitoring of the various LAN9312 functions through the System Control and Status Registers CSRs . These registers are accessible to the host via the Host Bus Interface and allow direct and indirect access to all the LAN9312 functions. For a full list of all System CSR’s and their descriptions, refer to Section "System Control and Status Registers". Interrupt support The HBI supports a variety of interrupt sources. Individual interrupts can be monitored and enabled/disabled via registers within the System CSRs for output on the IRQ pin. For more information on interrupts, refer to Chapter 5, "System Interrupts," on page For a list of all HBI related pins, refer to Table on page 30 in Chapter 3, Pin Description and Configuration. Host Memory Mapping The host memory map has two unique modes normal operation mode, and direct FIFO access mode. During normal operation, the base address decode map is as described in Figure on page 166, allowing access to the full range of System Management CSRs and the TX/RX Data and Status FIFOs. This is the default mode of operation. The second mode of operation is the direct FIFO access mode. In direct FIFO access mode, all host write operations are to the TX Data FIFO and all host read operations are from the RX Data FIFO. Refer to Section "Direct FIFO Access Mode," on page 167 for additional information. Host Endianess The LAN9312 supports big and little endian host byte ordering based upon the END_SEL pin. When END_SEL is low, host access is little endian. When END_SEL is high, host access is big endian. In a typical application, END_SEL is connected to a high-order address line, making endian selection address based. This highly flexible interface provides mixed endian access for registers and memory for both PIO and host DMA access. As an example, PIO transfers to/from the System CSRs can utilize a different byte ordering than host DMA transactions to/from the RX and TX Data FIFOs. All internal busses are 32-bit with little endian byte ordering. Logic within the host bus interface reorders bytes based on the state of the endian select signal END_SEL . SMSC LAN9312 DATASHEET High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Data path operations for the supported endian configurations are illustrated in Figure "Little Endian Byte Ordering" and Figure "Big Endian Byte Ordering". 32-BIT LITTLE ENDIAN END_SEL = 0 INTERNAL ORDER 24 23 16 15 24 23 16 15 HOST DATA BUS Figure Little Endian Byte Ordering 32-BIT BIG ENDIAN END_SEL = 1 INTERNAL ORDER 24 23 16 15 24 23 16 15 HOST DATA BUS Figure Big Endian Byte Ordering DATASHEET SMSC LAN9312 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Host Interface Timing This section details the characteristics and special restrictions of the various supported host cycles. For detailed timing specifications on supported PIO read/write operations, refer to Section "AC Specifications". The LAN9312 supports the following host cycles: Read Cycles PIO Reads nCS or nRD controlled PIO Burst Reads nCS or nRD controlled RX Data FIFO Direct PIO Reads nCS or nRD controlled RX Data FIFO Direct PIO Burst Reads nCS or nRD controlled Write Cycles PIO Writes nCS or nWR controlled TX Data FIFO Direct PIO Writes nCS or nWR controlled Special Situations Reset Ending During a Read Cycle If a reset condition terminates during an active read cycle, the tail end of the read cycle will be ignored by the LAN9312. Writes Following a Reset Following any reset, writes from the host bus are ignored until after a read cycle is performed. Special Restrictions on Back-to Back Write-Read Cycles It is important to note that there are specific restrictions on the timing of back-to-back host write-read operations. These restrictions concern reading the host control registers after any write cycle to the LAN9312. In some cases there is a delay between writing to the LAN9312, and the subsequent side effect change in the control register value . For example, when writing to the TX Data FIFO, it takes up to 135ns for the level indication to change in the TX FIFO Information Register TX_FIFO_INF . In order to prevent the host from reading stale data after a write operation, minimum wait periods have been established. These periods are specified in Table The host processor is required to wait the specified period of time after any write to the LAN9312 before reading the resource specified in the table. These wait periods are for read operations that immediately follow any write cycle. Note that the required wait period is dependant upon the register being read after the write. Performing “dummy” reads of the Byte Order Test Register BYTE_TEST register is a convenient way to guarantee that the minimum write-to-read timing restriction is met. Table shows the number of dummy reads that are required before reading the register indicated. The number of BYTE_TEST reads in this table is based on the minimum timing for Tcyc 45ns . For microprocessors with slower busses the number of reads may be reduced as long as the total time is equal to, or greater than the time specified in the table. Note that dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met. SMSC LAN9312 DATASHEET High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table Read After Write Timing Rules REGISTER NAME RX Data FIFO RX Status FIFO RX Status FIFO PEEK TX Status FIFO TX Status FIFO PEEK ID_REV IRQ_CFG INT_STS INT_EN BYTE_TEST FIFO_INT RX_CFG TX_CFG HW_CFG RX_DP_CTRL RX_FIFO_INF TX_FIFO_INF PMT_CTRL GPT_CFG GPT_CNT FREE_RUN RX_DROP MAC_CSR_CMD MAC_CSR_DATA AFC_CFG 1588_CLOCK_HI_RX_CAPTURE_1 1588_CLOCK_LO_RX_CAPTURE_1 1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_1 1588_SRC_UUID_LO_RX_CAPTURE_1 1588_CLOCK_HI_TX_CAPTURE_1 MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE IN NS 0 135 90 45 0 45 0 135 315 45 135 180 0 45 0 NUMBER OF BYTE_TEST READS ASSUMING TCYC OF 45NS 0 3 2 1 0 1 0 3 7 1 3 4 0 1 0 DATASHEET SMSC LAN9312 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table Read After Write Timing Rules continued REGISTER NAME 1588_CLOCK_LO_TX_CAPTURE_1 1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_1 1588_SRC_UUID_LO_TX_CAPTURE_1 1588_CLOCK_HI_RX_CAPTURE_2 1588_CLOCK_LO_RX_CAPTURE_2 1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_2 1588_SRC_UUID_LO_RX_CAPTURE_2 1588_CLOCK_HI_TX_CAPTURE_2 1588_CLOCK_LO_TX_CAPTURE_2 1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_2 1588_SRC_UUID_LO_TX_CAPTURE_2 1588_CLOCK_HI_RX_CAPTURE_MII 1588_CLOCK_LO_RX_CAPTURE_MII 1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_MII 1588_SRC_UUID_LO_RX_CAPTURE_MII 1588_CLOCK_HI_TX_CAPTURE_MII 1588_CLOCK_LO_TX_CAPTURE_MII 1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_MII 1588_SRC_UUID_LO_TX_CAPTURE_MII 1588_CLOCK_HI_CAPTURE_GPIO_8 1588_CLOCK_LO_CAPTURE_GPIO_8 1588_CLOCK_HI_CAPTURE_GPIO_9 1588_CLOCK_LO_CAPTURE_GPIO_9 1588_CLOCK_HI 1588_CLOCK_LO 1588_CLOCK_ADDEND 1588_CLOCK_TARGET_HI 1588_CLOCK_TARGET_LO 1588_CLOCK_TARGET_RELOAD_HI 1588_CLOCK_TARGET_RELOAD_LO 1588_AUX_MAC_HI MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE IN NS 0 45 Table below illustrates the byte ordering of the HMAC_ADDRL/SWITCH_MAC_ADDRL and HMAC_ADDRH/SWITCH_MAC_ADDRH registers with respect to the reception of the Ethernet physical address. Also shown is the correlation between the EEPROM addresses and HMAC_ADDRL/SWITCH_MAC_ADDRL and HMAC_ADDRH/SWITCH_MAC_ADDRH registers. Table EEPROM Byte Ordering and Register Correlation EEPROM Address 01h 02h 03h 04h 05h 06h Register Locations Written HMAC_ADDRL[7:0] SWITCH_MAC_ADDRL[7:0] HMAC_ADDRL[15:8] SWITCH_MAC_ADDRL[15:8] HMAC_ADDRL[23:16] SWITCH_MAC_ADDRL[23:16] HMAC_ADDRL[31:24] SWITCH_MAC_ADDRL[31:24] HMAC_ADDRH[7:0] SWITCH_MAC_ADDRH[7:0] HMAC_ADDRH[15:8] SWITCH_MAC_ADDRH[15:8] Order of Reception on Ethernet 1st 2nd 3rd 4th 5th 6th For example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the HMAC_ADDRL and HMAC_ADDRH registers would be programmed as shown in Figure The values required to automatically load this configuration from the EEPROM are also shown. SMSC LAN9312 DATASHEET High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 31 24 23 16 15 HMAC_ADDRH / SWITCH_MAC_ADDRH 31 24 23 16 15 HMAC_ADDRL / SWITCH_MAC_ADDRL 06h BCh 05h 9Ah 04h 78h 03h 56h 02h 34h 01h 12h 00h A5h EEPROM Figure Example EEPROM MAC Address Setup Note By convention, the right nibble of the left most byte of the Ethernet address in this example, the 2 of the 12h is the most significant nibble and is transmitted/received first. For more information on the EEPROM and EEPROM Loader, refer to Section "I2C/Microwire Master EEPROM Controller," on page FIFOs The LAN9312 contains four host-accessible FIFOs TX Status, RX Status, TX Data, and RX Data and two internal inaccessible Host MAC TX/RX MIL FIFO’s TX MIL FIFO, RX MIL FIFO . TX/RX FIFOs The TX/RX Data and Status FIFOs store the incoming and outgoing address and data information, acting as a conduit between the host bus interface HBI and the Host MAC. The sizes of these FIFOs are configurable via the Hardware Configuration Register HW_CFG register to the ranges described in Table Refer to Section "FIFO Memory Allocation Configuration" for additional information. The RX and TX FIFOs related register definitions can be found in section "Host MAC & FIFO’s". The TX and RX Data FIFOs have the base address of 00h and 20h respectively. However, each FIFO is also accessible at seven additional contiguous memory locations, as can be seen in Figure The Host may access the TX or RX Data FIFOs at any of these alias port locations, as they all function identically and contain the same data. This alias port addressing is implemented to allow hosts to burst through sequential addresses. The TX and RX Status FIFOs can each be read from two register locations the Status FIFO Port, and the Status FIFO PEEK. The TX and RX Status FIFO Ports 48h and 40h respectively will perform a destructive read, popping the data from the TX or RX Status FIFO. The TX and RX Status FIFO PEEK register locations 4Ch and 44h respectively allow a non-destructive read of the top oldest location of the FIFOs. Proper use of the TX/RX Data and Status FIFOs, including the correct data formatting is described in detail in Section "TX Data Path Operation," on page 122 and Section "RX Data Path Operation," on page MIL FIFOs The MAC Interface Layer MIL , within the Host MAC, contains a 2KB transmit and a 128 Byte receive FIFO which are separate from the TX and RX FIFOs. These MIL FIFOs are not directly accessible from the HBI. The differentiation between the TX/RX FIFOs and the TX/RX MIL FIFOs is that once the transmit or receive packets are in the MIL FIFOs, the host no longer can control or access the TX or RX data. The MIL FIFOs are essentially the working buffers of the Host MAC logic. In the case of DATASHEET SMSC LAN9312 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet reception, the data must be moved into the RX FIFOs before the host can access the data. For TX operations, the MIL operates in store-and-forward mode and will queue an entire frame before beginning transmission. As space in the TX MIL FIFO frees, data is moved into it from the TX Data FIFO. Depending on the size of the frames to be transmitted, the Host MAC can hold up to two Ethernet frames. This is in addition to any TX data that may be queued in the TX Data FIFO. Conversely, as data is received, it is moved from the Host MAC to the RX MIL FIFO, and then into the RX Data FIFO. When the RX Data FIFO fills up, data will continue to collect in the RX MIL FIFO. If the RX MIL FIFO fills up and overruns, subsequent RX frames will be lost until room is made in the RX Data FIFO. For each frame of data that is lost, the Host MAC RX Dropped Frames Counter Register RX_DROP is incremented. RX and TX MIL FIFO levels are not visible to the host processor and operate independent of the TX/RX FIFOs. FIFO levels set for the TX/RX Data and Status FIFOs do not take into consideration the MIL FIFOs. FIFO Memory Allocation Configuration TX and RX FIFO space is configurable through the Hardware Configuration Register HW_CFG . The user must select the FIFO allocation by setting the TX FIFO Size TX_FIF_SZ field in the Hardware Configuration Register HW_CFG . The TX_FIF_SZ field selects the total allocation for the TX data path, including the TX Status FIFO size. The TX Status FIFO size is fixed at 512 Bytes 128 TX Status DWORDs . The TX Status FIFO length is subtracted from the total TX FIFO size with the remainder being the TX Data FIFO Size. The minimum size of the TX FIFOs is 2KB TX Data and TX Status FIFOs combined . Note that TX Data FIFO space includes both commands and payload data. This read-only register can be used to determine the byte ordering of the current configuration. Byte ordering is a function of the host data bus width and endianess. Refer to Section "Host Endianess," on page 99 for additional information on byte ordering. Note This register can be read while the LAN9312 is in the reset or not ready states. The BYTE_TEST register can optionally be used as a dummy read register when assuring minimum write-to-read or read-to-read timing. Refer to Section "Special Restrictions on Back-to Back Write-Read Cycles," on page 101 and Section "Special Restrictions on Back-to-Back Read Cycles," on page 105 for additional information. BITS 31:0 DESCRIPTION Byte Test BYTE_TEST This field reflects the current byte ordering TYPE RO DEFAULT 87654321h DATASHEET SMSC LAN9312 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Hardware Configuration Register HW_CFG Offset: 074h Size: 32 bits This register allows the configuration of various hardware features including TX/RX FIFO sizes, Host MAC transmit threshold properties, and software reset. A detailed explanation of the allowable settings for FIFO memory allocation can be found in Section "FIFO Memory Allocation Configuration," on page Note This register can be polled while the LAN9312 is in the reset or not ready state READY bit is cleared . BITS 31:28 RESERVED 27 Device Ready When set, this bit indicates that the LAN9312 is ready to be accessed. Upon power-up, nRST reset, soft reset, or digital reset, the host processor may interrogate this field as an indication that the LAN9312 has stabilized and is fully active. This bit can cause an interrupt if enabled. Note: With the exception of the HW_CFG, PMT_CTRL, BYTE_TEST, and RESET_CTL registers, read access to any internal resources is forbidden while the READY bit is cleared. Writes to any address are invalid until this bit is set. Note This bit is identical to bit 0 of the Power Management Control Register PMT_CTRL . TYPE RO DEFAULT 0b 26 AMDIX_EN Strap State Port 2 This bit reflects the state of the auto_mdix_strap_2 strap that connects to the PHY. The strap value is loaded with the level of the auto_mdix_strap_2 during reset and can be re-written by the EEPROM Loader. The strap value can be overridden by bit 15 and 13 of the Port 2 PHY Special Control/Status Indication Register Section 25 AMDIX_EN Strap State Port 1 This bit reflects the state of the auto_mdix_strap_1 strap that connects to the PHY. The strap value is loaded with the level of the auto_mdix_strap_1 during reset and can be re-written by the EEPROM Loader. The strap value can be overridden by bit 15 and 13 of the Port 1 PHY Special Control/Status Indication Register Section 24:22 RESERVED 21 RESERVED - This bit must be written with 0b for proper operation. 20 Must Be One MBO . This bit must be set to ‘1’ for normal device operation. R/W Note Note SMSC LAN9312 This read/write register contains the upper 16-bits of the physical address of the Host MAC. The contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM Loader if a programmed EEPROM is detected. The least significant byte of this register bits [7:0] is loaded from address 05h of the EEPROM. The second byte bits [15:8] is loaded from address 06h of the EEPROM. Section "Host MAC Address," on page 119 details the byte ordering of the HMAC_ADDRL and HMAC_ADDRH registers with respect to the reception of the Ethernet physical address. Please refer to Section "I2C/Microwire Master EEPROM Controller," on page 137 for more information on the EEPROM Loader. BITS 31:16 RESERVED 15:0 Physical Address [47:32] This field contains the upper 16-bits 47:32 of the Physical Address of the Host MAC. The content of this field is undefined until loaded from the EEPROM at power-on. The host can update the contents of this field after the initialization process has completed. TYPE RO R/W DEFAULT - FFFFh DATASHEET SMSC LAN9312 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Host MAC Address Low Register HMAC_ADDRL Offset: Size: 32 bits This read/write register contains the lower 32-bits of the physical address of the Host MAC. The contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM Loader if a programmed EEPROM is detected. The least significant byte of this register bits [7:0] is loaded from address 01h of the EEPROM. The most significant byte of this register is loaded from address 04h of the EEPROM. Section "Host MAC Address," on page 119 details the byte ordering of the HMAC_ADDRL and HMAC_ADDRH registers with respect to the reception of the Ethernet physical address. Please refer to Section "I2C/Microwire Master EEPROM Controller," on page 137 for more information on the EEPROM Loader. BITS 31:0 DESCRIPTION Physical Address [31:0] This field contains the lower 32-bits 31:0 of the Physical Address of the Host MAC. The content of this field is undefined until loaded from the EEPROM at power-on. The host can update the contents of this field after the initialization process has completed. TYPE R/W DEFAULT SMSC LAN9312 DATASHEET High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Host MAC Multicast Hash Table High Register HMAC_HASHH Offset: Size: 32 bits The 64-bit Multicast table is used for group address filtering. For hash filtering, the contents of the destination address in the incoming frame is used to index the contents of the Hash table. The most significant bit determines the register to be used Hi/Low , while the other five bits determine the bit within the register. A value of selects Bit 0 of the Multicast Hash Table Lo register and a value of selects the Bit 31 of the Multicast Hash Table Hi register. If the corresponding bit is 1, then the multicast frame is accepted. Otherwise, it is rejected. If the “Pass All Multicast” MCPAS bit of the Host MAC Control Register HMAC_CR is set, then all multicast frames are accepted regardless of the multicast hash values. The Multicast Hash Table High register contains the higher 32 bits of the hash table and the Multicast Hash Table Low register contains the lower 32 bits of the hash table. Refer to Section "Address Filtering," on page 114 for more information on address filtering. This table determines if the Host MAC accepts the packets from the switch fabric. The switch fabric address table and configuration determine the packets that get sent to the Host MAC. BITS 31:0 DESCRIPTION Upper 32-bits of the 64-bit Hash Table TYPE R/W DEFAULT DATASHEET SMSC LAN9312 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Host MAC Multicast Hash Table Low Register HMAC_HASHL Offset: Size: 32 bits This read/write register defines the lower 32-bits of the Multicast Hash Table. Please refer to the Host MAC Multicast Hash Table High Register HMAC_HASHH and Section "Address Filtering" for more information. BITS 31:0 DESCRIPTION Lower 32-bits of the 64-bit Hash Table TYPE R/W DEFAULT SMSC LAN9312 DATASHEET High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Host MAC MII Access Register HMAC_MII_ACC Offset: Size: 32 bits This read/write register is used in conjunction with the Host MAC MII Data Register HMAC_MII_DATA to access the internal PHY registers. Refer to Section "Ethernet PHY Control and Status Registers" for a list of accessible PHY registers and PHY address information. BITS Fixed Priority Queue Servicing When set, output queues are serviced with a fixed priority ordering. When cleared, output queues are serviced with a weighted round robin ordering. Egress Rate Enable When set, egress rate pacing is enabled. Bits 4,3,2 correspond to switch ports 2,1,0 respectively. Drop on Yellow When this bit is set, packets that exceed the Ingress Committed Burst Size colored Yellow are subjected to random discard. Note: See Section "Switch Engine Ingress Rate Command Register SWE_INGRSS_RATE_CMD ," on page 395 for information on configuring the Ingress Committed Burst Size. Drop on Red When this bit is set, packets that exceed the Ingress Excess Burst Size colored Red are discarded. Note: See Section "Switch Engine Ingress Rate Command Register SWE_INGRSS_RATE_CMD ," on page 395 for information on configuring the Ingress Excess Burst Size. TYPE RO R/W R/W R/W R/W DEFAULT 0b DATASHEET SMSC LAN9312 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Buffer Manager Drop Level Register BM_DROP_LVL Register #: 1C01h Size: This register configures the overall buffer usage limits. 32 bits BITS 31:16 15:8 RESERVED Drop Level Low These bits specify the buffer limit that can be used per ingress port during times when 2 or 3 ports are active. Each buffer is 128 bytes. Note A port is “active” when 36 buffers are in use for that port. Drop Level High These bits specify the buffer limit that can be used per ingress port during times when 1 port is active. Each buffer is 128 bytes. Note A port is “active” when 36 buffers are in use for that port. TYPE RO R/W DEFAULT - SMSC LAN9312 DATASHEET High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Buffer Manager Flow Control Pause Level Register BM_FC_PAUSE_LVL Register #: 1C02h Size: 32 bits This register configures the buffer usage level when a Pause frame or backpressure is sent. BITS 31:16 15:8 RESERVED Pause Level Low These bits specify the buffer usage level during times when 2 or 3 ports are active. Each buffer is 128 bytes. Note A port is “active” when 36 buffers are in use for that port. Pause Level High These bits specify the buffer usage level during times when 1 port is active. Each buffer is 128 bytes. Note A port is “active” when 36 buffers are in use for that port. TYPE RO R/W Changed “Refer to the LAN9312 application note for additional connection information.” to “Refer to the LAN9312 reference schematic for additional connection information.” in the VDD18TX1, VDD18TX2, VDD18PLL, VDD33IO, VDD18CORE, VDD33A1, VDD33A2, and VDD33BIAS pin descriptions. Updated ordering codes to include tape and reel options. Updated 128-XVTQFP package dimensions and figures. Added note descriptions tsotaEtiEng_S“IDf AI2Canisd EE_SCL selected, pin an external pull-up is required when using an EEPROM and is recommended if no EEPROM is attached.” Added note to EEDO/EEPROM_TYPE pin doer uulsl-idnogwan Microwire resistor is recommended on this pin.” Clarified default values using binary. Added note to IFG Config field description Note IFG Config values less than 15 are unsupported. Corrected MIIBZY bit type to read only, selfclearing Corrected rightmost column title to “TX FLOW CONTROL ENABLE” Updated figure shading. Standard SMSC formatting applied. SMSC LAN9312 DATASHEET High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet CORRECTION Section "EEPROM Command Register E2P_CMD ," on page 197 Corrected CFG_LOADED bit type from “RO” to “R/WC” Section "Clock Circuit," on page 454 Changed max ESR value from 30 to 50 Ohms and corrected typos in operating temerpature range. Fixed various typos Port x PHY Special Control/Status Register PHY_SPECIAL_CONTROL _STATUS_x on page 307 Updated RESERVED bits 11:5 definition to “RESERVED - Write as ignore on read”, changed default to and made field R/W. Wake-Up Frame Detection section of Host MAC Chapter and MAC_CR register description Added note at end of WUFF section and to the BCAST bit of the MAC_CR register stating When wake-up frame detection is enabled via the WUEN bit of the HMAC_WUCSR register, a broadcast wake-up frame will wake-up the device despite the state of the Disable Broadcast Frames BCAST bit in the HMAC_CR register. HMAC_WUCSR register Fixed error in GUE bit description “....the MAC Address [1:0] bits...” changed to “...the MAC Address [0] bits....”. Port x PHY Auto-Negotiation Advertisement Register PHY_AN_ADV_x on page 294 Bits 15 and 9 made RESERVED. Section "Clock Circuit," on page 454 Changed minimum drive level from 0.5mW to 300uW DATASHEET SMSC LAN9312

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LAN9312

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

PRODUCT FEATURES

Highlights

High performance and full featured 2 port switch with VLAN, QoS packet prioritization, Rate Limiting, IGMP monitoring and management functions

Easily interfaces to most 32-bit embedded CPU’s Unique Virtual PHY feature simplifies software
development by mimicking the multiple switch ports as a single port MAC/PHY Integrated IEEE 1588 Hardware Time Stamp Unit

Target Applications

Cable, satellite, and IP set-top boxes Digital televisions Digital video recorders VoIP/Video phone systems Home gateways Test/Measurement equipment Industrial automation systems

Key Benefits

Ethernet Switch Fabric
32K buffer RAM 1K entry forwarding table Port based IEEE 802.1Q VLAN support 16 groups

Programmable IEEE 802.1Q tag insertion/removal IEEE 802.1d spanning tree protocol support QoS/CoS Packet prioritization
4 dynamic QoS queues per port Input priority determined by VLAN tag, DA lookup,

TOS, DIFFSERV or port default value Programmable class of service map based on input
priority Remapping of 802.1Q priority field on per port basis Programmable rate limiting at the ingress/egress
ports with random early discard, per port / priority IGMP v1/v2/v3 monitoring for Multicast packet filtering Programmable filter by MAC address

Switch Management

Port mirroring/monitoring/sniffing ingress and/or egress traffic on any ports or port pairs

Fully compliant statistics MIB gathering counters Control registers configurable on-the-fly

Datasheet

Ports
2 internal 10/100 PHYs with HP Auto-MDIX support Fully compliant with IEEE standards 10BASE-T and 100BASE-TX support Full and half duplex support Full duplex flow control Backpressure forced collision half duplex flow control Automatic flow control based on programmable levels Automatic 32-bit CRC generation and checking Automatic payload padding 2K Jumbo packet support Programmable interframe gap, flow control pause value Full transmit/receive statistics Auto-negotiation Automatic MDI/MDI-X Loop-back mode

High-performance host bus interface

Provides in-band network communication path Access to management registers Simple, SRAM-like interface 32-bit data bus Big, little, and mixed endian support Large TX and RX FIFO’s for high latency applications Programmable water marks and threshold levels Host interrupt support

IEEE 1588 Hardware Time Stamp Unit

Global 64-bit tunable clock Master or slave mode per port Time stamp on TX or RX of Sync and Delay_req
packets per port, Timestamp on GPIO 64-bit timer comparator event generation GPIO or IRQ

Comprehensive Power Management Features

Wake on LAN Wake on link status change energy detect Magic packet wakeup indicator event signal

Other Features

General Purpose Timer Serial EEPROM interface I2C master or MicrowireTM
master for non-managed configuration Programmable GPIOs/LEDs

Single 3.3V power supply

Available in Commercial Temp. Range

SMSC LAN9312

DATASHEET

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet

Order Numbers LAN9312-NU For 128-Pin, VTQFP Lead-Free RoHS Compliant Package 0 TO 70°C Temp Range LAN9312-NZW For 128-Pin, XVTQFP Lead-Free RoHS Compliant Package 0 TO 70°C Temp Range LAN9312-NU-TR For 128-Pin, VTQFP Lead-Free RoHS Compliant Package 0 TO 70°C Temp Range LAN9312-NZW-TR For 128-Pin, XVTQFP Lead-Free RoHS Compliant Package 0 TO 70°C Temp Range

TR indicates tape & reel option.

This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit
Figure Internal LAN9312 Block Diagram. 21 Figure System Block Diagram. 25 Figure LAN9312 128-VTQFP Pin Assignments TOP VIEW 26 Figure LAN9312 128-XVTQFP Pin Assignments TOP VIEW . 27 Figure PME and PME_INT Signal Generation 47 Figure Functional Interrupt Register Hierarchy 50 Figure Switch Fabric CSR Write Access Flow Diagram 57 Figure Switch Fabric CSR Read Access Flow Diagram 58 Figure ALR Table Entry Structure 63 Figure Switch Engine Transmit Queue Selection 67 Figure Switch Engine Transmit Queue Calculation. 68 Figure VLAN Table Entry Structure. 70 Figure Switch Engine Ingress Flow Priority Selection 73 Figure Switch Engine Ingress Flow Priority Calculation 73 Figure Hybrid Port Tagging and Un-tagging 80 Figure Port x PHY Block Diagram 83 Figure 100BASE-TX Transmit Data Path 84 Figure 100BASE-TX Receive Data Path. 87 Figure Direct Cable Connection vs. Cross-Over Cable Connection 93 Figure Little Endian Byte Ordering 100 Figure Big Endian Byte Ordering. 100 Figure Functional Timing for PIO Read Operation 106 Figure Functional Timing for PIO Burst Read Operation. 107 Figure Functional Timing for RX Data FIFO Direct PIO Read Operation 108 Figure Functional Timing for RX Data FIFO Direct PIO Burst Read Operation 109 Figure Functional Timing for PIO Write Operation 110 Figure Functional Timing for TX Data FIFO Direct PIO Write Operation 111 Figure VLAN Frame 114 Figure Example EEPROM MAC Address Setup 120 Figure Simplified Host TX Flow Diagram 123 Figure TX Buffer Format 124 Figure TX Example 129 Figure TX Example 130 Figure Host Receive Routine Using Interrupts 133 Figure Host Receive Routine Using Polling 133 Figure RX Packet Format 135 Figure EEPROM Access Flow Diagram 139 Figure I2C Cycle 141 Figure I2C EEPROM Addressing 141 Figure I2C EEPROM Byte Read 142 Figure I2C EEPROM Sequential Byte Reads 142 Figure I2C EEPROM Byte Write 143 Figure EEPROM ERASE Cycle 145 Figure EEPROM ERAL Cycle 146 Figure EEPROM EWDS Cycle 146 Figure 10.10EEPROM EWEN Cycle 147 Figure 10.11EEPROM READ Cycle 147 Figure 10.12EEPROM WRITE Cycle 148 Figure 10.13EEPROM WRAL Cycle 148 Figure 10.14EEPROM Loader Flow Diagram 150 Figure IEEE 1588 Block Diagram 155 Figure IEEE 1588 Message Time Stamp Point. 156

DATASHEET

SMSC LAN9312

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Figure LAN9312 Base Register Memory Map. 166 Figure Output Equivalent Test Load 444 Figure nRST Reset Pin Timing 445 Figure Power-On Configuration Strap Latching Timing. 446 Figure PIO Read Cycle Timing 447 Figure PIO Burst Read Cycle Timing 448 Figure RX Data FIFO Direct PIO Read Cycle Timing 449 Figure RX Data FIFO Direct PIO Burst Read Cycle Timing 450 Figure PIO Write Cycle Timing 451 Figure TX Data FIFO Direct PIO Write Cycle Timing 452 Figure 15.10Microwire Timing 453 Figure 128-VTQFP Package Definition 455 Figure 128-VTQFP Recommended PCB Land Pattern. 456 Figure 128-XVTQFP Package Definition. 457 Figure 128-XVTQFP Recommended PCB Land Pattern 458

SMSC LAN9312

DATASHEET

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet

List of Tables
Table Buffer Types 18 Table Register Bit Types 19 Table LAN Port 1 Pins 28 Table LAN Port 2 Pins 29 Table LAN Port 1 & 2 Power and Common Pins 29 Table Host Bus Interface Pins 30 Table EEPROM Pins 31 Table Dedicated Configuration Strap Pins. 33 Table Miscellaneous Pins 34 Table PLL Pins 35 Table Core and I/O Power and Ground Pins 35 Table No-Connect Pins 35 Table Reset Sources and Affected LAN9312 Circuitry 37 Table Soft-Strap Configuration Strap Definitions. 41 Table Hard-Strap Configuration Strap Definitions 46 Table Switch Fabric Flow Control Enable Logic 59 Table Spanning Tree States 70 Table Typical Ingress Rate Settings 72 Table Typical Broadcast Rate Settings 74 Table Typical Egress Rate Settings. 78 Table Default PHY Serial MII Addressing 82 Table 4B/5B Code Table 85 Table PHY Interrupt Sources. 94 Table Read After Write Timing Rules 102 Table Read After Read Timing Rules 105 Table Address Filtering Modes 115 Table Wake-Up Frame Filter Register Structure 117 Table Filter i Byte Mask Bit Definitions 117 Table Filter i Command Bit Definitions 117 Table Filter i Offset Bit Definitions 118 Table Filter i CRC-16 Bit Definitions 118 Table EEPROM Byte Ordering and Register Correlation 119 Table TX/RX FIFO Configurable Sizes 121 Table Valid TX/RX FIFO Allocations 122 Table TX Command 'A' Format 125 Table TX Command 'B' Format 126 Table TX DATA Start Offset 126 Table I2C/Microwire Master Serial Management Pins Characteristics. 137 Table I2C EEPROM Size Ranges 140 Table Microwire EEPROM Size Ranges 144 Table Microwire Command Set for 7 Address Bits 144 Table Microwire Command Set for 9 Address Bits 144 Table Microwire Command Set for 11 Address Bits 145 Table EEPROM Contents Format Overview 149 Table EEPROM Configuration Bits 151 Table IEEE 1588 Message Type Detection. 156 Table Time Stamp Capture Delay 157 Table PTP Multicast Addresses. 158 Table Typical IEEE 1588 Clock Addend Values 159 Table LED Operation as a Function of LED_CFG[9:8] 164 Table System Control and Status Registers 168 Table Backpressure Duration Bit Mapping 190

DATASHEET

SMSC LAN9312

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

SMSC LAN9312

DATASHEET

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet

Chapter 1 Preface

General Terms
100BT ADC ALR BLW BM BPDU

Byte CSMA/CD CSR CTR DA DWORD EPC FCS

FIFO FSM GPIO HBI

HBIC

Host IGMP Inbound Level-Triggered Sticky Bit
lsb MDI MDIX
100BASE-T 100Mbps Fast Ethernet, IEEE 802.3u Analog-to-Digital Converter Address Logic Resolution Baseline Wander Buffer Manager - Part of the switch fabric Bridge Protocol Data Unit - Messages which carry the Spanning Tree Protocol information 8-bits Carrier Sense Multiple Access / Collision Detect Control and Status Registers Counter Destination Address 32-bits EEPROM Controller Frame Check Sequence - The extra checksum characters added to the end of an Ethernet frame, used for error detection and correction. First In First Out buffer Finite State Machine General Purpose I/O Host Bus Interface. The physical bus connecting the LAN9312 to the host. Also referred to as the Host Bus. Host Bus Interface Controller. The hardware module that interfaces the LAN9312 to the HBI. External system Includes processor, application software, etc. Internet Group Management Protocol Refers to data input to the LAN9312 from the host This type of status bit is set whenever the condition that it represents is asserted. The bit remains set until the condition is no longer true, and the status bit is cleared by writing a zero. Least Significant Bit Least Significant Byte Medium Dependant Interface Media Independent Interface with Crossover

DATASHEET

SMSC LAN9312

MII MIIM MIL MLT-3
msb NRZI

N/A NC OUI Outbound PIO cycle PISO PLL PTP RESERVED

RTC SA SFD

SIPO SMI SQE SSD UDP

UUID WORD

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet

Media Independent Interface Media Independent Interface Management MAC Interface Layer Multi-Level Transmission Encoding 3-Levels . A tri-level encoding method where a change in the logic level represents a code bit “1” and the logic output remaining at the same level represents a code bit Most Significant Bit Most Significant Byte Non Return to Zero Inverted. This encoding method inverts the signal for a “1” and leaves the signal unchanged for a “0” Not Applicable No Connect Organizationally Unique Identifier Refers to data output from the LAN9312 to the host Program I/O cycle. An SRAM-like read or write cycle on the HBI. Parallel In Serial Out Phase Locked Loop Precision Time Protocol Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must always be zero for write operations. Unless otherwise noted, values are not guaranteed when reading reserved bits. Unless otherwise noted, do not read or write to reserved addresses. Real-Time Clock Source Address Start of Frame Delimiter - The 8-bit value indicating the end of the preamble of an Ethernet frame. Serial In Parallel Out Serial Management Interface Signal Quality Error also known as “heartbeat” Start of Stream Delimiter User Datagram Protocol - A connectionless protocol run on top of IP networks Universally Unique IDentifier 16-bits

SMSC LAN9312

DATASHEET

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet

Buffer Types

Table describes the pin buffer type notation used in Chapter 3, "Pin Description and Configuration," on page 26 and throughout this document.

Table Buffer Types

BUFFER TYPE IS O8

OD8 O12 OD12 PU

AI AO AIO ICLK OCLK P

Schmitt-triggered Input

Output with 8mA sink and 8mA source

Open-drain output with 8mA sink

Output with 12mA sink and 12mA source

Open-drain output with 12mA sink
When a transmit queue is non-empty, it is serviced and the packet is read from the buffer RAM and sent to the transmit MAC. If there are multiple queues that require servicing, one of two methods may be used fixed priority ordering, or weighted round-robin ordering. If the Fixed Priority Queue Servicing bit in the Buffer Manager Configuration Register BM_CFG is set, a strict order, fixed priority is selected. Transmit queue 3 has the highest priority, followed by 2, 1, and If the Fixed Priority Queue Servicing bit in the Buffer Manager Configuration Register BM_CFG is cleared, a weighted roundrobin order is followed. Assuming all four queues are non-empty, the service is weighted with a 9:4:2:1 ratio queue The servicing is blended to avoid burstiness e.g. queue 3, then queue 2, then queue 3, etc. .

Egress Rate Limiting Leaky Bucket

For egress rate limiting, the leaky bucket algorithm is used on each output priority queue. For each output port, the bandwidth that is used by each priority queue can be limited. If any egress queue receives packets faster than the specified egress rate, packets will be accumulated in the packet memory. After the memory is used, packet dropping or flow control will be triggered.

Note Egress rate limiting occurs before the Transmit Priority Queue Servicing, such that a lower priority queue will be serviced if a higher priority queue is being rate limited.

The egress limiting is enabled per priority queue. After a packet is selected to be sent, its length is recorded. The switch then waits a programmable amount of time, scaled by the packet length, before servicing that queue once again. The amount of time per byte is programmed into the Buffer Manager Egress Rate registers refer to Section through Section for detailed register definitions . The value programmed is in approximately 20 nS per byte increments. Typical values are listed in Table When a port is transmitting at 10 Mbps, any setting above 39 has the effect of not limiting the rate.

Table Typical Egress Rate Settings

EGRESS RATE SETTING
0-3 4 5 6 7 9 12 19 39 78 158 396 794 1589 3973 7947

TIME PER BYTE
80 nS 100 nS 120 nS 140 nS 160 nS 200 nS 260 nS 400 nS 800 nS 1580 nS 3180 nS 7940 nS 15900 nS 31800 nS 79480 nS 158960 nS

BANDWIDTH 64 BYTE PACKET
76 Mbps Note 66 Mbps 55 Mbps 48 Mbps 42 Mbps 34 Mbps 26 Mbps 17 Mbps 870 Kbps 440 Kbps 220 Kbps 87 Kbps 44 Kbps

BANDWIDTH 512 BYTE PACKET
96 Mbps Note 78 Mbps 65 Mbps 56 Mbps 49 Mbps 39 Mbps 30 Mbps 20 Mbps 10 Mbps 5 Mbps 990 Kbps 490 Kbps 250 Kbps 98 Kbps 49 Kbps

BANDWIDTH 1518 BYTE PACKET
99 Mbps Note 80 Mbps 67 Mbps 57 Mbps 50 Mbps 40 Mbps 31 Mbps 20 Mbps 10 Mbps 5 Mbps 1 Mbps 500 Kbps 250 Kbps 100 Kbps 50 Kbps

DATASHEET

SMSC LAN9312

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Datasheet

Note These are the unlimited max bandwidths when IFG and preamble are taken into account.

Adding, Removing, and Changing VLAN Tags

Based on the port configuration and the received packet formation, a VLAN tag can be added to, removed from, or modified in a packet. There are four received packet type cases non-tagged, prioritytagged, normal-tagged, and CPU special-tagged. There are also four possible settings for an egress port dumb, access, hybrid, and CPU. In addition, each VLAN table entry can specify the removal of the VLAN tag the entry’s un-tag bit .

The tagging/un-tagging rules are specified as follows:

Dumb Port - This port type generally does not change the tag. When a received packet is non-tagged, priority-tagged, or normal-tagged, the packet passes untouched. When a packet is received special-tagged from a CPU port, the special tag is removed.

Access Port - This port type generally does not support tagging. When a received packet in non-tagged, the packet passes untouched. When a received packet is priority-tagged or normal-tagged, the tag is removed. When a received packet is special-tagged from a CPU port, the special tag is removed.

CPU Port - Packets transmitted from this port type generally contain a special tag. Special tags are described in detail in Section "Host CPU Port Special Tagging," on page

Hybrid Port - Generally, this port type supports a mix of normal-tagged and non-tagged packets. It is the most complex, but most flexible port type.

For clarity, the following details the incoming un-tag instruction. As described in Section "VLAN Support," on page 70, the un-tag instruction is one of three un-tag bits from the applicable entry in the VLAN table, selected by the ingress port number. The entry in the VLAN table is either the VLAN from the received packet or the ingress ports default VID.

When a received packet is non-tagged, a new VLAN tag is added if two conditions are met. First, the Insert Tag bit for the egress port in the Buffer Manager Egress Port Type Register BM_EGRSS_PORT_TYPE must be set. Second, the un-tag instruction associated with the ingress ports default VID must be cleared. The VLAN tag that is added will have a VID and Priority taken from the ingress ports default VID and priority.

When a received packet is priority-tagged, either the tag is removed or it is modified. If the un-tag instruction associated with the ingress ports default VID is set, then the tag is removed. Otherwise, the tag is modified. The VID of the new VLAN tag is changed to the ingress ports default VID. If the Change Priority bit in the Buffer Manager Egress Port Type Register BM_EGRSS_PORT_TYPE for the egress port is set, then the Priority field of the new VLAN tag is also changed to the ingress ports default priority.

When a received packet is normal-tagged, either the tag is removed, modified, or passed. If the un-tag instruction associated with the VID in the received packet is set, then the tag is removed. Else, if the Change Tag bit in the Buffer Manager Egress Port Type Register BM_EGRSS_PORT_TYPE for the egress port is clear, the packet is untouched. Else, if both the Change VLAN ID and the Change Priority bits in the Buffer Manager Egress Port Type Register BM_EGRSS_PORT_TYPE for the egress port are clear, the packet passes untouched. Otherwise, the tag is modified. If the Change VLAN ID bit for the egress port is set, the VOD of the new VLAN tag is changed to the egress ports default ID. If the Change Priority bit for the egress port is set, the Priority field of the new VLAN is changed to the egress ports default priority.

When a packet is received special-tagged from a CPU port, the special tag is removed.

SMSC LAN9312

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Hybrid tagging is summarized in Figure

Receive Tag Type

Non-tagged

Normal Tagged Priority Tagged

Insert Tag
Host data bus endianess control The HBI supports dynamic selection of big and little endian host byte ordering based on the END_SEL input pin. This highly flexible interface provides mixed endian access for registers and memory.

Direct FIFO access modes When the FIFO_SEL input pin is high during host access, all host write operations are to the TX data FIFO and all host read operations are from the RX data FIFOs. This feature facilitates operation with host DMA controllers that do not support FIFO operations.

System CSR’s The HBI allows for configuration and monitoring of the various LAN9312 functions through the System Control and Status Registers CSRs . These registers are accessible to the host via the Host Bus Interface and allow direct and indirect access to all the LAN9312 functions. For a full list of all System CSR’s and their descriptions, refer to Section "System Control and Status Registers".

Interrupt support The HBI supports a variety of interrupt sources. Individual interrupts can be monitored and enabled/disabled via registers within the System CSRs for output on the IRQ pin. For more information on interrupts, refer to Chapter 5, "System Interrupts," on page

For a list of all HBI related pins, refer to Table on page 30 in Chapter 3, Pin Description and Configuration.

Host Memory Mapping

The host memory map has two unique modes normal operation mode, and direct FIFO access mode. During normal operation, the base address decode map is as described in Figure on page 166, allowing access to the full range of System Management CSRs and the TX/RX Data and Status FIFOs. This is the default mode of operation. The second mode of operation is the direct FIFO access mode. In direct FIFO access mode, all host write operations are to the TX Data FIFO and all host read operations are from the RX Data FIFO. Refer to Section "Direct FIFO Access Mode," on page 167 for additional information.

Host Endianess
The LAN9312 supports big and little endian host byte ordering based upon the END_SEL pin. When END_SEL is low, host access is little endian. When END_SEL is high, host access is big endian. In a typical application, END_SEL is connected to a high-order address line, making endian selection address based. This highly flexible interface provides mixed endian access for registers and memory for both PIO and host DMA access. As an example, PIO transfers to/from the System CSRs can utilize a different byte ordering than host DMA transactions to/from the RX and TX Data FIFOs.
All internal busses are 32-bit with little endian byte ordering. Logic within the host bus interface reorders bytes based on the state of the endian select signal END_SEL .

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Data path operations for the supported endian configurations are illustrated in Figure "Little Endian Byte Ordering" and Figure "Big Endian Byte Ordering".
32-BIT LITTLE ENDIAN

END_SEL = 0

INTERNAL ORDER
24 23
16 15
24 23
16 15

HOST DATA BUS
Figure Little Endian Byte Ordering
32-BIT BIG ENDIAN

END_SEL = 1

INTERNAL ORDER
24 23
16 15
24 23
16 15

HOST DATA BUS
Figure Big Endian Byte Ordering

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Datasheet

Host Interface Timing

This section details the characteristics and special restrictions of the various supported host cycles. For detailed timing specifications on supported PIO read/write operations, refer to Section "AC Specifications". The LAN9312 supports the following host cycles:

Read Cycles PIO Reads nCS or nRD controlled PIO Burst Reads nCS or nRD controlled RX Data FIFO Direct PIO Reads nCS or nRD controlled RX Data FIFO Direct PIO Burst Reads nCS or nRD controlled

Write Cycles PIO Writes nCS or nWR controlled TX Data FIFO Direct PIO Writes nCS or nWR controlled

Special Situations

Reset Ending During a Read Cycle

If a reset condition terminates during an active read cycle, the tail end of the read cycle will be ignored by the LAN9312.

Writes Following a Reset

Following any reset, writes from the host bus are ignored until after a read cycle is performed.

Special Restrictions on Back-to Back Write-Read Cycles

It is important to note that there are specific restrictions on the timing of back-to-back host write-read operations. These restrictions concern reading the host control registers after any write cycle to the LAN9312. In some cases there is a delay between writing to the LAN9312, and the subsequent side effect change in the control register value . For example, when writing to the TX Data FIFO, it takes up to 135ns for the level indication to change in the TX FIFO Information Register TX_FIFO_INF .

In order to prevent the host from reading stale data after a write operation, minimum wait periods have been established. These periods are specified in Table The host processor is required to wait the specified period of time after any write to the LAN9312 before reading the resource specified in the table. These wait periods are for read operations that immediately follow any write cycle. Note that the required wait period is dependant upon the register being read after the write.

Performing “dummy” reads of the Byte Order Test Register BYTE_TEST register is a convenient way to guarantee that the minimum write-to-read timing restriction is met. Table shows the number of dummy reads that are required before reading the register indicated. The number of BYTE_TEST reads in this table is based on the minimum timing for Tcyc 45ns . For microprocessors with slower busses the number of reads may be reduced as long as the total time is equal to, or greater than the time specified in the table. Note that dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met.

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Table Read After Write Timing Rules

REGISTER NAME RX Data FIFO RX Status FIFO

RX Status FIFO PEEK TX Status FIFO

TX Status FIFO PEEK ID_REV IRQ_CFG INT_STS INT_EN

BYTE_TEST FIFO_INT RX_CFG TX_CFG HW_CFG

RX_DP_CTRL RX_FIFO_INF TX_FIFO_INF

PMT_CTRL GPT_CFG GPT_CNT FREE_RUN RX_DROP MAC_CSR_CMD MAC_CSR_DATA AFC_CFG 1588_CLOCK_HI_RX_CAPTURE_1 1588_CLOCK_LO_RX_CAPTURE_1 1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_1 1588_SRC_UUID_LO_RX_CAPTURE_1 1588_CLOCK_HI_TX_CAPTURE_1

MINIMUM WAIT TIME FOR READ FOLLOWING ANY

WRITE CYCLE IN NS 0
135 90 45 0 45 0 135 315 45 135 180 0 45 0

NUMBER OF BYTE_TEST READS

ASSUMING TCYC OF 45NS 0 3 2 1 0 1 0 3 7 1 3 4 0 1 0

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Table Read After Write Timing Rules continued

REGISTER NAME 1588_CLOCK_LO_TX_CAPTURE_1 1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_1 1588_SRC_UUID_LO_TX_CAPTURE_1 1588_CLOCK_HI_RX_CAPTURE_2 1588_CLOCK_LO_RX_CAPTURE_2 1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_2 1588_SRC_UUID_LO_RX_CAPTURE_2 1588_CLOCK_HI_TX_CAPTURE_2 1588_CLOCK_LO_TX_CAPTURE_2 1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_2 1588_SRC_UUID_LO_TX_CAPTURE_2 1588_CLOCK_HI_RX_CAPTURE_MII 1588_CLOCK_LO_RX_CAPTURE_MII 1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_MII 1588_SRC_UUID_LO_RX_CAPTURE_MII 1588_CLOCK_HI_TX_CAPTURE_MII 1588_CLOCK_LO_TX_CAPTURE_MII 1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_MII 1588_SRC_UUID_LO_TX_CAPTURE_MII 1588_CLOCK_HI_CAPTURE_GPIO_8 1588_CLOCK_LO_CAPTURE_GPIO_8 1588_CLOCK_HI_CAPTURE_GPIO_9 1588_CLOCK_LO_CAPTURE_GPIO_9
1588_CLOCK_HI 1588_CLOCK_LO 1588_CLOCK_ADDEND 1588_CLOCK_TARGET_HI 1588_CLOCK_TARGET_LO 1588_CLOCK_TARGET_RELOAD_HI 1588_CLOCK_TARGET_RELOAD_LO 1588_AUX_MAC_HI

MINIMUM WAIT TIME FOR READ FOLLOWING ANY

WRITE CYCLE IN NS 0 45
Table below illustrates the byte ordering of the HMAC_ADDRL/SWITCH_MAC_ADDRL and HMAC_ADDRH/SWITCH_MAC_ADDRH registers with respect to the reception of the Ethernet physical address. Also shown is the correlation between the EEPROM addresses and HMAC_ADDRL/SWITCH_MAC_ADDRL and HMAC_ADDRH/SWITCH_MAC_ADDRH registers.
Table EEPROM Byte Ordering and Register Correlation

EEPROM Address 01h 02h 03h 04h 05h 06h

Register Locations Written HMAC_ADDRL[7:0]

SWITCH_MAC_ADDRL[7:0] HMAC_ADDRL[15:8]

SWITCH_MAC_ADDRL[15:8] HMAC_ADDRL[23:16]

SWITCH_MAC_ADDRL[23:16] HMAC_ADDRL[31:24]

SWITCH_MAC_ADDRL[31:24] HMAC_ADDRH[7:0]

SWITCH_MAC_ADDRH[7:0] HMAC_ADDRH[15:8]

SWITCH_MAC_ADDRH[15:8]

Order of Reception on Ethernet 1st 2nd 3rd 4th 5th 6th

For example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the HMAC_ADDRL and HMAC_ADDRH registers would be programmed as shown in Figure The values required to automatically load this configuration from the EEPROM are also shown.

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31 24 23 16 15

HMAC_ADDRH / SWITCH_MAC_ADDRH
31 24 23 16 15

HMAC_ADDRL / SWITCH_MAC_ADDRL
06h BCh 05h 9Ah 04h 78h 03h 56h 02h 34h 01h 12h 00h A5h

EEPROM

Figure Example EEPROM MAC Address Setup

Note By convention, the right nibble of the left most byte of the Ethernet address in this example, the 2 of the 12h is the most significant nibble and is transmitted/received first.

For more information on the EEPROM and EEPROM Loader, refer to Section "I2C/Microwire Master EEPROM Controller," on page

FIFOs

The LAN9312 contains four host-accessible FIFOs TX Status, RX Status, TX Data, and RX Data and two internal inaccessible Host MAC TX/RX MIL FIFO’s TX MIL FIFO, RX MIL FIFO .

TX/RX FIFOs

The TX/RX Data and Status FIFOs store the incoming and outgoing address and data information, acting as a conduit between the host bus interface HBI and the Host MAC. The sizes of these FIFOs are configurable via the Hardware Configuration Register HW_CFG register to the ranges described in Table Refer to Section "FIFO Memory Allocation Configuration" for additional information. The RX and TX FIFOs related register definitions can be found in section "Host MAC & FIFO’s".

The TX and RX Data FIFOs have the base address of 00h and 20h respectively. However, each FIFO is also accessible at seven additional contiguous memory locations, as can be seen in Figure The Host may access the TX or RX Data FIFOs at any of these alias port locations, as they all function identically and contain the same data. This alias port addressing is implemented to allow hosts to burst through sequential addresses.

The TX and RX Status FIFOs can each be read from two register locations the Status FIFO Port, and the Status FIFO PEEK. The TX and RX Status FIFO Ports 48h and 40h respectively will perform a destructive read, popping the data from the TX or RX Status FIFO. The TX and RX Status FIFO PEEK register locations 4Ch and 44h respectively allow a non-destructive read of the top oldest location of the FIFOs.

Proper use of the TX/RX Data and Status FIFOs, including the correct data formatting is described in detail in Section "TX Data Path Operation," on page 122 and Section "RX Data Path Operation," on page

MIL FIFOs

The MAC Interface Layer MIL , within the Host MAC, contains a 2KB transmit and a 128 Byte receive FIFO which are separate from the TX and RX FIFOs. These MIL FIFOs are not directly accessible from the HBI. The differentiation between the TX/RX FIFOs and the TX/RX MIL FIFOs is that once the transmit or receive packets are in the MIL FIFOs, the host no longer can control or access the TX or RX data. The MIL FIFOs are essentially the working buffers of the Host MAC logic. In the case of

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reception, the data must be moved into the RX FIFOs before the host can access the data. For TX operations, the MIL operates in store-and-forward mode and will queue an entire frame before beginning transmission.

As space in the TX MIL FIFO frees, data is moved into it from the TX Data FIFO. Depending on the size of the frames to be transmitted, the Host MAC can hold up to two Ethernet frames. This is in addition to any TX data that may be queued in the TX Data FIFO.

Conversely, as data is received, it is moved from the Host MAC to the RX MIL FIFO, and then into the RX Data FIFO. When the RX Data FIFO fills up, data will continue to collect in the RX MIL FIFO. If the RX MIL FIFO fills up and overruns, subsequent RX frames will be lost until room is made in the RX Data FIFO. For each frame of data that is lost, the Host MAC RX Dropped Frames Counter Register RX_DROP is incremented.

RX and TX MIL FIFO levels are not visible to the host processor and operate independent of the TX/RX FIFOs. FIFO levels set for the TX/RX Data and Status FIFOs do not take into consideration the MIL FIFOs.

FIFO Memory Allocation Configuration

TX and RX FIFO space is configurable through the Hardware Configuration Register HW_CFG . The user must select the FIFO allocation by setting the TX FIFO Size TX_FIF_SZ field in the Hardware Configuration Register HW_CFG . The TX_FIF_SZ field selects the total allocation for the TX data path, including the TX Status FIFO size. The TX Status FIFO size is fixed at 512 Bytes 128 TX Status DWORDs . The TX Status FIFO length is subtracted from the total TX FIFO size with the remainder being the TX Data FIFO Size. The minimum size of the TX FIFOs is 2KB TX Data and TX Status FIFOs combined . Note that TX Data FIFO space includes both commands and payload data.
This read-only register can be used to determine the byte ordering of the current configuration. Byte ordering is a function of the host data bus width and endianess. Refer to Section "Host Endianess," on page 99 for additional information on byte ordering.

Note This register can be read while the LAN9312 is in the reset or not ready states.

The BYTE_TEST register can optionally be used as a dummy read register when assuring minimum write-to-read or read-to-read timing. Refer to Section "Special Restrictions on Back-to Back Write-Read Cycles," on page 101 and Section "Special Restrictions on Back-to-Back Read Cycles," on page 105 for additional information.

BITS 31:0
DESCRIPTION Byte Test BYTE_TEST This field reflects the current byte ordering

TYPE RO

DEFAULT
87654321h

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Hardware Configuration Register HW_CFG

Offset:
074h

Size:
32 bits

This register allows the configuration of various hardware features including TX/RX FIFO sizes, Host MAC transmit threshold properties, and software reset. A detailed explanation of the allowable settings for FIFO memory allocation can be found in Section "FIFO Memory Allocation Configuration," on page

Note This register can be polled while the LAN9312 is in the reset or not ready state READY bit is cleared .

BITS
31:28 RESERVED
27 Device Ready When set, this bit indicates that the LAN9312 is ready to be accessed. Upon power-up, nRST reset, soft reset, or digital reset, the host processor may interrogate this field as an indication that the LAN9312 has stabilized and is fully active.

This bit can cause an interrupt if enabled.

Note:

With the exception of the HW_CFG, PMT_CTRL, BYTE_TEST, and RESET_CTL registers, read access to any internal resources is forbidden while the READY bit is cleared. Writes to any address are invalid until this bit is set.

Note This bit is identical to bit 0 of the Power Management Control Register PMT_CTRL .

TYPE RO

DEFAULT 0b
26 AMDIX_EN Strap State Port 2

This bit reflects the state of the auto_mdix_strap_2 strap that connects to
the PHY. The strap value is loaded with the level of the auto_mdix_strap_2
during reset and can be re-written by the EEPROM Loader. The strap value
can be overridden by bit 15 and 13 of the Port 2 PHY Special Control/Status

Indication Register Section
25 AMDIX_EN Strap State Port 1

This bit reflects the state of the auto_mdix_strap_1 strap that connects to
the PHY. The strap value is loaded with the level of the auto_mdix_strap_1
during reset and can be re-written by the EEPROM Loader. The strap value
can be overridden by bit 15 and 13 of the Port 1 PHY Special Control/Status

Indication Register Section
24:22 RESERVED
21 RESERVED - This bit must be written with 0b for proper operation.
20 Must Be One MBO . This bit must be set to ‘1’ for normal device operation. R/W

Note

Note

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This read/write register contains the upper 16-bits of the physical address of the Host MAC. The contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM Loader if a programmed EEPROM is detected. The least significant byte of this register bits [7:0] is loaded from address 05h of the EEPROM. The second byte bits [15:8] is loaded from address 06h of the EEPROM. Section "Host MAC Address," on page 119 details the byte ordering of the HMAC_ADDRL and HMAC_ADDRH registers with respect to the reception of the Ethernet physical address. Please refer to Section "I2C/Microwire Master EEPROM Controller," on page 137 for more information on the EEPROM Loader.

BITS
31:16 RESERVED
15:0 Physical Address [47:32] This field contains the upper 16-bits 47:32 of the Physical Address of the Host MAC. The content of this field is undefined until loaded from the EEPROM at power-on. The host can update the contents of this field after the initialization process has completed.

TYPE RO R/W

DEFAULT -

FFFFh

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Host MAC Address Low Register HMAC_ADDRL

Offset:

Size:
32 bits
This read/write register contains the lower 32-bits of the physical address of the Host MAC. The contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM Loader if a programmed EEPROM is detected. The least significant byte of this register bits [7:0] is loaded from address 01h of the EEPROM. The most significant byte of this register is loaded from address 04h of the EEPROM. Section "Host MAC Address," on page 119 details the byte ordering of the HMAC_ADDRL and HMAC_ADDRH registers with respect to the reception of the Ethernet physical address. Please refer to Section "I2C/Microwire Master EEPROM Controller," on page 137 for more information on the EEPROM Loader.

BITS 31:0

DESCRIPTION Physical Address [31:0] This field contains the lower 32-bits 31:0 of the Physical Address of the Host MAC. The content of this field is undefined until loaded from the EEPROM at power-on. The host can update the contents of this field after the initialization process has completed.

TYPE R/W

DEFAULT

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Host MAC Multicast Hash Table High Register HMAC_HASHH

Offset:

Size:
32 bits

The 64-bit Multicast table is used for group address filtering. For hash filtering, the contents of the destination address in the incoming frame is used to index the contents of the Hash table. The most significant bit determines the register to be used Hi/Low , while the other five bits determine the bit within the register. A value of selects Bit 0 of the Multicast Hash Table Lo register and a value of selects the Bit 31 of the Multicast Hash Table Hi register.

If the corresponding bit is 1, then the multicast frame is accepted. Otherwise, it is rejected. If the “Pass All Multicast” MCPAS bit of the Host MAC Control Register HMAC_CR is set, then all multicast frames are accepted regardless of the multicast hash values.

The Multicast Hash Table High register contains the higher 32 bits of the hash table and the Multicast Hash Table Low register contains the lower 32 bits of the hash table. Refer to Section "Address Filtering," on page 114 for more information on address filtering.

This table determines if the Host MAC accepts the packets from the switch fabric. The switch fabric address table and configuration determine the packets that get sent to the Host MAC.

BITS 31:0

DESCRIPTION Upper 32-bits of the 64-bit Hash Table

TYPE R/W

DEFAULT

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Host MAC Multicast Hash Table Low Register HMAC_HASHL

Offset:

Size:
32 bits

This read/write register defines the lower 32-bits of the Multicast Hash Table. Please refer to the Host MAC Multicast Hash Table High Register HMAC_HASHH and Section "Address Filtering" for more information.

BITS 31:0

DESCRIPTION Lower 32-bits of the 64-bit Hash Table

TYPE R/W

DEFAULT

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Host MAC MII Access Register HMAC_MII_ACC

Offset:

Size:
32 bits

This read/write register is used in conjunction with the Host MAC MII Data Register HMAC_MII_DATA to access the internal PHY registers. Refer to Section "Ethernet PHY Control and Status Registers" for a list of accessible PHY registers and PHY address information.

BITS
Fixed Priority Queue Servicing When set, output queues are serviced with a fixed priority ordering. When cleared, output queues are serviced with a weighted round robin ordering.

Egress Rate Enable When set, egress rate pacing is enabled. Bits 4,3,2 correspond to switch ports 2,1,0 respectively.

Drop on Yellow When this bit is set, packets that exceed the Ingress Committed Burst Size colored Yellow are subjected to random discard.

Note:

See Section "Switch Engine Ingress Rate Command Register SWE_INGRSS_RATE_CMD ," on page 395 for information on configuring the Ingress Committed Burst Size.

Drop on Red When this bit is set, packets that exceed the Ingress Excess Burst Size colored Red are discarded.

Note:

See Section "Switch Engine Ingress Rate Command Register SWE_INGRSS_RATE_CMD ," on page 395 for information on configuring the Ingress Excess Burst Size.

TYPE RO R/W R/W R/W R/W

DEFAULT 0b

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Buffer Manager Drop Level Register BM_DROP_LVL

Register #:
1C01h

Size:

This register configures the overall buffer usage limits.
32 bits

BITS
31:16 15:8

RESERVED

Drop Level Low These bits specify the buffer limit that can be used per ingress port during times when 2 or 3 ports are active. Each buffer is 128 bytes. Note A port is “active” when 36 buffers are in use for that port.

Drop Level High These bits specify the buffer limit that can be used per ingress port during times when 1 port is active. Each buffer is 128 bytes. Note A port is “active” when 36 buffers are in use for that port.

TYPE RO R/W

DEFAULT -

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Buffer Manager Flow Control Pause Level Register BM_FC_PAUSE_LVL

Register #:
1C02h

Size:
32 bits

This register configures the buffer usage level when a Pause frame or backpressure is sent.

BITS
31:16 15:8

RESERVED

Pause Level Low These bits specify the buffer usage level during times when 2 or 3 ports are active. Each buffer is 128 bytes. Note A port is “active” when 36 buffers are in use for that port.

Pause Level High These bits specify the buffer usage level during times when 1 port is active. Each buffer is 128 bytes. Note A port is “active” when 36 buffers are in use for that port.

TYPE RO R/W
Changed “Refer to the LAN9312 application note for additional connection information.” to “Refer to the LAN9312 reference schematic for additional connection information.” in the VDD18TX1, VDD18TX2, VDD18PLL, VDD33IO, VDD18CORE, VDD33A1, VDD33A2, and VDD33BIAS pin descriptions. Updated ordering codes to include tape and reel options. Updated 128-XVTQFP package dimensions and figures.

Added note descriptions
tsotaEtiEng_S“IDf AI2Canisd

EE_SCL selected,
pin an
external
pull-up is required when using an EEPROM and is
recommended if no EEPROM is attached.”

Added note to EEDO/EEPROM_TYPE pin
doer uulsl-idnogwan

Microwire resistor is
recommended on this pin.”

Clarified default values using binary.

Added note to IFG Config field description Note IFG Config values less than 15 are
unsupported.

Corrected MIIBZY bit type to read only, selfclearing

Corrected rightmost column title to “TX FLOW CONTROL ENABLE” Updated figure shading. Standard SMSC formatting applied.

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CORRECTION

Section "EEPROM Command Register E2P_CMD ," on page 197

Corrected CFG_LOADED bit type from “RO” to “R/WC”

Section "Clock Circuit," on page 454

Changed max ESR value from 30 to 50 Ohms and corrected typos in operating temerpature range.

Fixed various typos

Port x PHY Special Control/Status Register PHY_SPECIAL_CONTROL _STATUS_x on page 307

Updated RESERVED bits 11:5 definition to “RESERVED - Write as ignore on read”, changed default to and made field R/W.

Wake-Up Frame Detection section of Host MAC Chapter and MAC_CR register description

Added note at end of WUFF section and to the BCAST bit of the MAC_CR register stating When wake-up frame detection is enabled via the WUEN bit of the HMAC_WUCSR register, a broadcast wake-up frame will wake-up the device despite the state of the Disable Broadcast Frames BCAST bit in the HMAC_CR register.

HMAC_WUCSR register

Fixed error in GUE bit description “....the MAC Address [1:0] bits...” changed to “...the MAC Address [0] bits....”.

Port x PHY Auto-Negotiation Advertisement Register PHY_AN_ADV_x on page 294

Bits 15 and 9 made RESERVED.

Section "Clock Circuit," on page 454

Changed minimum drive level from 0.5mW to 300uW

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SMSC LAN9312

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived LAN9312-NU Datasheet file may be downloaded here without warranties.

Datasheet ID: LAN9312-NU 648123