SY100S360FC

SY100S360FC Datasheet

SY100S360 FINAL

Part	Datasheet
SY100S360FC	SY100S360FC (pdf)

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DUAL PARITY CHECKER/ GENERATOR SY100S360 FINAL s Max. propagation delay of 2200ps s IEE min. of s Industry standard 100K ECL levels s Extended supply voltage option: VEE = to s Voltage and temperature compensation for improved noise immunity s Internal input pull-down resistors s 15% faster than Fairchild 300K s Approximately 30% lower power than Fairchild 300K s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC packages The SY100S360 is a dual parity checker/generator and is designed for use in high-performance ECL systems. The inputs are segmented into two groups of nine inputs each and the parity output is at a logic LOW when an even number of inputs are at a logic HIGH. In each group, one of the nine inputs Ia, Ib has a shorter propagation delay and, therefore, is ideal as the expansion input for parity generation of wider data. A Compare output C is also provided which allows comparison of two 8-bit words. A logic LOW on the C output indicates a match. The inputs on this device have pull-down resistors. PIN CONFIGURATIONS I5a I4a I3a VEES I2a I1a I0a BLOCK DIAGRAM I0a I1a I2a I3a I4a I5a I6a I7a Ia I0b I1b I2b I3b I4b I5b I6b I7b Ib 11 10 9 8 7 6 5 I6a 12 I7a 13 VEE 14 VEES 15 I0b 16 Top View PLCC J28-1 VCCA I1b 17 I2b 18 26 Zb 19 20 21 22 23 24 25 I3b I4b I5b VEES I6b I7b Ib I2b I1b I0b VEE I7a I6a 24 23 22 21 20 19 Top View 16 I3a Flatpack F24-1 7 8 9 10 11 12 Zb C VCC VCCA Za Ia Issue Date July, 1999 Micrel PIN NAMES Pin Ia, Ib, Ina, Inb Za Zb C VEES VCCA Function Data Inputs n = Parity Odd Outputs Compare Output VEE Substrate VCCO for ECL Outputs SY100S360 TRUTH TABLE 1 Sum of High Inputs Output Z Even PRODUCT ORDERING CODE Ordering Code SY100S360FC SY100S360JC SY100S360JCTR Package Type F24-1 J28-1 J28-1 Operating Range Commercial Micrel 24 LEAD CERPACK F24-1 SY100S360 Micrel 28 LEAD PLCC J28-1 SY100S360 MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA TEL + 1 408 980-9191 FAX + 1 408 914-7878 WEB This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. 2000 Micrel Incorporated 5

PDF Datasheet Preview

DUAL PARITY CHECKER/ GENERATOR

SY100S360 FINAL
s Max. propagation delay of 2200ps s IEE min. of s Industry standard 100K ECL levels s Extended supply voltage option:

VEE = to s Voltage and temperature compensation for improved
noise immunity s Internal input pull-down resistors s 15% faster than Fairchild 300K s Approximately 30% lower power than Fairchild 300K s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC
packages

The SY100S360 is a dual parity checker/generator and is designed for use in high-performance ECL systems. The inputs are segmented into two groups of nine inputs each and the parity output is at a logic LOW when an even number of inputs are at a logic HIGH. In each group, one of the nine inputs Ia, Ib has a shorter propagation delay and, therefore, is ideal as the expansion input for parity generation of wider data.

A Compare output C is also provided which allows comparison of two 8-bit words. A logic LOW on the C output indicates a match. The inputs on this device have pull-down resistors.

PIN CONFIGURATIONS

I5a I4a I3a VEES I2a I1a I0a

BLOCK DIAGRAM

I0a I1a I2a I3a I4a I5a I6a I7a Ia

I0b I1b I2b I3b I4b I5b I6b I7b Ib
11 10 9 8 7 6 5

I6a 12

I7a 13

VEE 14 VEES 15

I0b 16

Top View PLCC J28-1

VCCA

I1b 17

I2b 18
26 Zb
19 20 21 22 23 24 25

I3b I4b I5b VEES I6b I7b Ib

I2b I1b I0b VEE I7a I6a
24 23 22 21 20 19

Top View 16 I3a

Flatpack F24-1
7 8 9 10 11 12

Zb C VCC VCCA Za Ia

Issue Date July, 1999

Micrel

PIN NAMES

Pin Ia, Ib, Ina, Inb Za Zb C VEES VCCA

Function Data Inputs n = Parity Odd Outputs Compare Output VEE Substrate VCCO for ECL Outputs

SY100S360

TRUTH TABLE 1

Sum of High Inputs

Output Z

Even
PRODUCT ORDERING CODE
Ordering Code

SY100S360FC SY100S360JC SY100S360JCTR

Package Type F24-1 J28-1 J28-1

Operating Range

Commercial

Micrel
24 LEAD CERPACK F24-1

SY100S360

Micrel
28 LEAD PLCC J28-1

SY100S360

MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA TEL + 1 408 980-9191 FAX + 1 408 914-7878 WEB

This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. 2000 Micrel Incorporated 5

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived SY100S360FC Datasheet file may be downloaded here without warranties.

Datasheet ID: SY100S360FC 647933