ATSAMG51N18A-AU

ATSAMG51N18A-AU Datasheet


Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode. Non Maskable Interrupt NMI

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ARM-based Flash MCU

SAM G51 Series DATASHEET

The Atmel SAM G51 series is a member of a family of Flash microcontrollers based on the high-performance 32-bit RISC processor with Floating Point Unit. It operates at a maximum speed of 48 MHz and features up to 256 Kbytes of Flash and up to 64 Kbytes of SRAM. The peripheral set includes one USART, two UARTs, two TWIs, one high-speed TWI, up to two SPIs, one three-channel generalpurpose 16-bit timer, one RTT and one 8-channel 12-bit ADC. The SAM G51 series is a general-purpose microcontroller with the best ratio in terms of reduced power consumption, processing power and optimized peripheral set. This enables the SAM G51 series to sustain a wide range of applications including consumer, industrial control, and PC peripherals. The device operates from 1.62V to 2V and is available in a 49-ball WLCSP or a 100lead LQFP package.

Core ARM Cortex-M4 up to 48 MHz Memory Protection Unit MPU DSP Instructions Floating Point Unit FPU instruction set

Memories 256 Kbytes embedded Flash 64 Kbytes embedded SRAM

System Embedded voltage regulator for single-supply operation Power-on reset POR and Watchdog for safe operation Quartz or ceramic resonator oscillators 3 to 20MHz power with failure detection and 32.768kHz for RTT or device clock High-precision 8/16/24MHz factory-trimmed internal RC oscillator. In-application trimming access for frequency adjustment Slow clock internal RC oscillator as permanent low-power mode device clock PLL range from 24 MHz to 48MHz for device clock Up to 18 peripheral DMA PDC channels 8 x 32-bit General-Purpose Backup Registers GPBR 16 external interrupt lines

Power consumption in active mode 103 µA/MHz running Fibonacci on SRAM

Low-power modes typical value Wait mode µA Wake-up time µs

Peripherals One USART with SPI Mode Two 2-wire UARTs Three Two-Wire Interface TWI modules featuring two fast mode TWI masters and one high-speed TWI slave One fast SPI at up to 24Mbit/s One three-channel 16-bit Timer/Counter TC with capture, waveform, compare and PWM modes One 32-bit Real-Time Timer and Real-Time Clock RTC

I/Os Up to 38 I/O lines with external interrupt capability edge or level sensitivity , debouncing, glitch filtering and on-die Series Resistor Termination. Individually Programmable Open-drain, Pull-up and pull-down resistor and Synchronous Output Two up to 25-bit PIO Controllers

Analog One 8-channel 12-bit ADC, up to 800 KSps

Package 49-ball WLCSP 100-lead LQFP

Industrial temperature operating range -40° C/+85° C

SAM G51 [DATASHEET]

Configuration Summary

Table 1-1 summarizes the configuration of the SAM G51 devices.

Table Configuration Summary

Feature Flash SRAM

SAM G51G18 256 Kbytes 64 Kbytes

Package Number of PIOs Event System

WLCSP49 38 Yes
12-bit ADC 16-bit Timer
8 channels Performance 800 KSps at 10-bit resolution 200 KSps at 11-bit resolution 50 KSps at 12-bit resolution
3 channels

PDC Channels

USART/UART
2 masters 400 Kbit/s and
1 slave Mbit/s

Note One with SPI module + one USART configured in SPI mode.

SAM G51N18 256 Kbytes 64 Kbytes LQFP100 38 Yes 8 channels Performance:
600 KSps at 10-bit resolution 150 KSps at 11-bit resolution 37 KSps at 12-bit resolution
3 channels 18 1/2
2 masters 400Kbits/s and 1 slave 3.4Mbit/s

SAM G51 [DATASHEET]

SAM G51 Block Diagram

Figure SAM G51 Block Diagram

TDI TDO TMS/STWCKD/ISOWJCTLAKGSEL

VDDIO VDDOUT

TST PCK0-PCK2

XIN XOUT WKUP0-15 XIN32 XOUT32 ERASE

VDDIO VDDCORE
The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory. Additional Memory Attributes

Shareable For a shareable memory region, the memory system provides data synchronization between bus masters in a system with multiple bus masters, for example, a processor with a DMA controller. Strongly-ordered memory is always shareable. If multiple bus masters can access a non-shareable memory region, the software must ensure data coherency between the bus masters.

Execute Never XN Means the processor prevents instruction accesses. A fault exception is generated only on execution of an instruction executed from an XN region.
Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing this does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses completing in program order, the software must insert a memory barrier instruction between the memory access instructions, see “Software Ordering of Memory Accesses”
However, the memory system does guarantee some ordering of accesses to Device and Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs before A2 in program order, the ordering of the memory accesses is described below.
Table Ordering of the Memory Accesses Caused by Two Instructions

Device Access

Strongly-

Normal

Non-
ordered

Access
shareable

Shareable

Access

Normal Access

Device access, non-shareable

Device access, shareable

Strongly-ordered access

Where:
Means that the memory system does not guarantee the ordering of the accesses.
< Means that accesses are observed in program order, that is, A1 is always observed before A2.

SAM G51 [DATASHEET] 45

Behavior of Memory Accesses The following table describes the behavior of accesses to each region in the memory map.

Table Memory Access Behavior

Address Range

Memory Region

Memory Type

XN Description

Code

Normal 1

Executable region for program code. Data can also be put here.

SRAM

Normal 1

Executable region for data. Code can also be put here. This region includes bit band and bit band alias areas,
see Table

Peripheral External RAM External device

Device 1

Normal 1 Device 1

This region includes bit band and bit band alias areas, see Table

Executable region for data

XN External Device memory

Private Peripheral Bus

Stronglyordered 1

This region includes the NVIC, system timer, and system control block.

Reserved

Device 1 XN Reserved

Note See “Memory Regions, Types and Attributes” for more information.

The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends that programs always use the Code region. This is because the processor has separate buses that enable instruction fetches and data accesses to occur simultaneously.

The MPU can override the default memory access behavior described in this section. For more information, see “Memory Protection Unit MPU ” Additional Memory Access Constraints For Shared Memory

When a system includes shared memory, some memory regions have additional access constraints, and some regions are subdivided, as Table 10-5 shows.

Table Memory Region Shareability Policies

Address Range

Memory Region Code SRAM Peripheral

Memory Type Normal 1 Normal 1 Device 1

External RAM

Normal 1

External device

Private Peripheral Bus Vendor-specific device

Device 1

Strongly-ordered 1 Device 1
Software Ordering of Memory Accesses

The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions. This is because:

The processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence.

The processor has multiple bus interfaces Memory or devices in the memory map have different wait states Some memory accesses are buffered or speculative.
“Memory System Ordering of Memory Accesses” describes the cases where the memory system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is critical, the software must include memory barrier instructions to force that ordering. The processor provides the following memory barrier instructions DMB

The Data Memory Barrier DMB instruction ensures that outstanding memory transactions complete before subsequent memory transactions. See “DMB” DSB

The Data Synchronization Barrier DSB instruction ensures that outstanding memory transactions complete before subsequent instructions execute. See “DSB” ISB

The Instruction Synchronization Barrier ISB ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. See “ISB” MPU Programming

Use a DSB followed by an ISB instruction or exception return to ensure that the new MPU configuration is used by subsequent instructions.

Bit-banding

A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions.

The memory map has two 32 MB alias regions that map to two 1 MB bit-band regions Accesses to the 32 MB SRAM alias region map to the 1 MB SRAM bit-band region, as shown in Table Accesses to the 32 MB peripheral alias region map to the 1 MB peripheral bit-band region, as shown in Table

Table SRAM Memory Bit-banding Regions

Address Range

Memory Region

SRAM bit-band region

SRAM bit-band alias

Instruction and Data Accesses

Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit-addressable through bit-band alias.

Data accesses to this region are remapped to bit-band region. A write operation is performed as read-modify-write. Instruction accesses are not remapped.

SAM G51 [DATASHEET] 47

Table Peripheral Memory Bit-banding Regions

Address Range

Memory Region

Instruction and Data Accesses

Peripheral bit-band alias

Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit-addressable through bit-band alias.

Peripheral bit-band region

Data accesses to this region are remapped to bit-band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted.

Notes A word access to the SRAM or peripheral bit-band alias regions map to a single bit in the SRAM or peripheral bitband region.

Bit-band accesses can use byte, halfword, or word transfers. The bit-band transfer size matches the transfer size of the instruction making the bit-band access.

The following formula shows how the alias region maps onto the bit-band region bit_word_offset = byte_offset x 32 + bit_number x 4 bit_word_addr = bit_band_base + bit_word_offset
where Bit_word_offset is the position of the target bit in the bit-band memory region. Bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit. Bit_band_base is the starting address of the alias region. Byte_offset is the number of the byte in the bit-band region that contains the targeted bit. Bit_number is the bit position, of the targeted bit.

Figure 10-4 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bit-band region:

The alias word at 0x23FFFFE0 maps to bit[0] of the bit-band byte at 0x23FFFFE0 = + +

The alias word at maps to bit[7] of the bit-band byte at = + +

The alias word at maps to bit[0] of the bit-band byte at = + 0*32 +

The alias word at 0x2200001C maps to bit[7] of the bit-band byte at 0x2200001C = 0*32 +

SAM G51 [DATASHEET] 48

Figure Bit-band Mapping
32 MB alias region
0x23FFFFEC 0x23FFFFE8 0x23FFFFE4 0x23FFFFE0
0x2200001C 0x22000018 0x22000014 0x22000010
1 MB SRAM bit-band region
76543210765432107654321076543210
DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before the DMB instruction are completed before any explicit memory accesses that appear, in program order, after the DMB instruction. DMB does not affect the ordering or execution of instructions that do not access memory.

Condition Flags

This instruction does not change the flags.

Examples DMB Data Memory Barrier

SAM G51 [DATASHEET]

Data Synchronization Barrier.

Syntax
where:
cond
is an optional condition code, see “Conditional Execution”

Operation

DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do not execute until the DSB instruction completes. The DSB instruction completes when all explicit memory accesses before it complete.

Condition Flags

This instruction does not change the flags.

Examples DSB Data Synchronisation Barrier

SAM G51 [DATASHEET]

Instruction Synchronization Barrier.

Syntax
where:
cond
is an optional condition code, see “Conditional Execution”

Operation

ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from memory again, after the ISB instruction has been completed.

Condition Flags

This instruction does not change the flags.

Examples ISB Instruction Synchronisation Barrier

SAM G51 [DATASHEET]

Move the contents of a special register to a general-purpose register.

Syntax Rd, spec_reg
where:
cond
is an optional condition code, see “Conditional Execution”
is the destination register.
spec_reg
can be any of APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.

Operation

Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR, for example to clear the Q flag.

In process swap code, the programmers model state of the process being swapped out must be saved, including relevant PSR contents. Similarly, the state of the process being swapped in must also be restored. These operations use MRS in the state-saving instruction sequence and MSR in the state-restoring instruction sequence.

Note BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction.

See “MSR”

Restrictions
Byte ordering scheme in which bytes of decreasing significance in a data word are stored at increasing addresses in memory. See also “Byte-invariant” , “Endianness” , “Little-endian LE ”

Memory in which a byte or halfword at a word-aligned address is the most significant byte or halfword within the word at that address, a byte at a halfword-aligned address is the most significant byte within the halfword at that address. See also “Little-endian memory”

Breakpoint

A breakpoint is a mechanism provided by debuggers to identify an instruction at which program execution is to be halted. Breakpoints are inserted by the programmer to enable inspection of register contents, memory locations, variable values at fixed points in the program execution to test that the program is operating correctly. Breakpoints are removed after the program is successfully tested.

SAM G51 [DATASHEET]

Byte-invariant

In a byte-invariant system, the address of each byte of memory remains unchanged when switching between little-endian and big-endian operation. When a data item larger than a byte is loaded from or stored to memory, the bytes making up that data item are arranged into the correct order depending on the endianness of the memory access. An ARM byte-invariant implementation also supports unaligned halfword and word memory accesses. It expects multi-word accesses to be word-aligned.

Condition field

A four-bit field in an instruction that specifies a condition under which the instruction can execute.

Conditional execution Context Coprocessor

If the condition code flags indicate that the corresponding condition is true when the instruction starts executing, it executes normally. Otherwise, the instruction does nothing.

The environment that each process operates in for a multitasking operating system. In ARM processors, this is limited to mean the physical address range that it can access in memory and the associated memory access permissions.

A processor that supplements the main processor. Cortex-M4 does not support any coprocessors.

Debugger

Direct Memory Access DMA Doubleword

A debugging system that includes a program, used to detect, locate, and correct software faults, together with custom hardware that supports software debugging.

An operation that accesses main memory directly, without the processor performing any accesses to the data concerned.

A 64-bit data item. The contents are taken as being an unsigned integer unless otherwise stated.

Doubleword-aligned Endianness

Exception

A data item having a memory address that is divisible by eight.
Byte ordering. The scheme that determines the order that successive bytes of a data word are stored in memory. An aspect of the system’s memory mapping. See also “Little-endian LE ” and “Big-endian BE ”

An event that interrupts program execution. When an exception occurs, the processor suspends the normal program flow and starts execution at the address indicated by the corresponding exception vector. The indicated address contains the first instruction of the handler for the exception. An exception can be an interrupt request, a fault, or a software-generated system exception. Faults include attempting an invalid memory access, attempting to execute an instruction in an invalid processor state, and attempting to execute an undefined instruction.

SAM G51 [DATASHEET]

Exception service routine

See “Interrupt handler”

Exception vector Flat address mapping

See “Interrupt vector”

A system of organizing memory in which each physical address in the memory space is the same as the corresponding virtual address.

Halfword Illegal instruction Implementation-defined

A 16-bit data item.

An instruction that is architecturally Undefined.

The behavior is not architecturally defined, but is defined and documented by individual implementations.

Implementation-specific

The behavior is not architecturally defined, and does not have to be documented by individual implementations. Used when there are a number of implementation options available and the option chosen does not affect software compatibility.

Index register

In some load and store instruction descriptions, the value of this register is used as an offset to be added to or subtracted from the base register value to form the address that is sent to memory. Some addressing modes optionally enable the index register value to be shifted prior to the addition or subtraction.

See also “Base register”

Instruction cycle count Interrupt handler Interrupt vector

Little-endian LE

The number of cycles that an instruction occupies the Execute stage of the pipeline.

A program that control of the processor is passed to when an interrupt occurs.

One of a number of fixed addresses in low memory, or in high memory if high vectors are configured, that contains the first instruction of the corresponding interrupt handler.
Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing addresses in memory. See also “Big-endian BE ” , “Byte-invariant” , “Endianness”

SAM G51 [DATASHEET]

Little-endian memory

Memory in which a byte or halfword at a word-aligned address is the least significant byte or halfword within the word at that address, a byte at a halfword-aligned address is the least significant byte within the halfword at that address.

See also “Big-endian memory”

Load/store architecture

Memory Protection Unit MPU Prefetching

A processor architecture where data-processing operations only operate on register contents, not directly on memory contents.

Hardware that controls access permissions to blocks of memory. An MPU does not perform any address translation.

In pipelined processors, the process of fetching instructions from memory to fill up the pipeline before the preceding instructions have finished executing. Prefetching an instruction does not mean that the instruction has to be executed.

Preserved Read Region Reserved

Preserved by writing the same value back that has been previously read from the same field on the same processor.

Reads are defined as memory operations that have the semantics of a load. Reads include the Thumb instructions LDM, LDR, LDRSH, LDRH, LDRSB, LDRB, and POP.

A partition of memory space.

A field in a control register or instruction format is reserved if the field is to be defined by the implementation, or produces Unpredictable results if the contents of the field are not zero. These fields are reserved for use in future extensions of the architecture or are implementation-specific. All reserved bits not used by the implementation must be written as 0 and read as

Thread-safe Thumb instruction Unaligned

In a multi-tasking environment, thread-safe functions use safeguard mechanisms when accessing shared resources, to ensure correct operation without the risk of shared access conflicts.

One or two halfwords that specify an operation for a processor to perform. Thumb instructions must be halfword-aligned.

A data item stored at an address that is not divisible by the number of bytes that defines the data size is said to be unaligned. For example, a word stored at an address that is not divisible by four.

SAM G51 [DATASHEET]

Undefined Unpredictable Warm reset

Word Write

Indicates an instruction that generates an Undefined instruction exception.

One cannot rely on the behavior. Unpredictable behavior must not represent security holes. Unpredictable behavior must not halt or hang the processor, or any parts of the system.

Also known as a core reset. Initializes the majority of the processor excluding the debug controller and debug logic. This type of reset is useful if debugging features of a processor.

A 32-bit data item.

Writes are defined as operations that have the semantics of a store. Writes include the Thumb instructions STM, STR, STRH, STRB, and PUSH.

SAM G51 [DATASHEET]

Debug and Test Features

The SAM G51 features a number of complementary debug and test capabilities. The Serial Wire/JTAG Debug Port SWJ-DP combining a Serial Wire Debug Port SW-DP and JTAG Debug Port JTAG-DP is used for standard debugging functions, such as downloading code and single-stepping through programs. It also embeds a serial wire trace.

Embedded Characteristics

Debug access to all memories and registers in the system, including Cortex-M4 register bank when the core is running, halted, or held in reset.

Serial Wire Debug Port SW-DP and Serial Wire JTAG Debug Port SWJ-DP debug access. Flash Patch and Breakpoint FPB unit for implementing breakpoints and code patches. Data Watchpoint and Trace DWT unit for implementing watchpoints, data tracing, and system profiling. Instrumentation Trace Macrocell ITM for support of printf style debugging. IEEE1149.1 JTAG Boundary-scan on all digital pins.

Figure Debug and Test Block Diagram

TMS TCK/SWCLK TDI

Boundary TAP

SWJ-DP

Reset and Test

JTAGSEL TDO/TRACESWO

POR TST

SAM G51 [DATASHEET]
Ordering Information
Table Ordering Codes for SAM G51 Devices
Ordering Code

Flash Kbytes

SAMG51G18A-UUT

SAMG51N18A-AU

Package Kbytes WLCSP49

LQFP100

Package Type Green

Temperature Operating Range

Industrial -40°C to 85°C

Industrial -40°C to 85°C

SAM G51 [DATASHEET]

In the tables that follow, the most recent version of the document appears first.

Table Doc. Date 20-Dec-13

Table Doc. Date 23-Jul-13

Table Doc. Date 08-Mar-13

SAM G51 [DATASHEET]

Table of Contents

Description 1

Features. 2

Configuration Summary 3

SAM G51 Block Diagram 4

Signal Description 5

Package and Pinout 7
49-ball WLCSP Pinout 7 100-lead LQFP Pinout 8

Power Considerations 9

Power Supplies 9 Voltage Regulator 9 Typical Powering Schematics 9 Functional Modes 10 Fast Start-up 12

Processor and Architecture 13

ARM Cortex-M4 Processor 13 APB/AHB Bridge 13 Peripheral DMA Controller 13 Debug and Test Features 14 Product Mapping. 15

Memories 16

Embedded Memories 16

System Controller 19

System Controller and Peripherals Mapping 19 Power-on Reset, Supply Monitor 19 Reset Controller 19 Supply Controller 19 Clock Generator 20 Power Management Controller 21 Watchdog Timer 21 SysTick Timer 22 Real-Time Timer 22 Real Time Clock 22 General-Purpose Backup Registers 22 Nested Vectored Interrupt Controller 22 Chip Identification 22 PIO Controllers 23 Peripheral Identifiers 24 Peripherals Signals Multiplexing on I/O Lines. 26

Real-Time Event Management 29

SAM G51 [DATASHEET]

Embedded Characteristics 29 Real-Time Event Mapping 29

ARM Cortex-M4 Processor 30

Description 30 Embedded Characteristics 31 Block Diagram. 31 Cortex-M4 Models. 32 Power Management 60 Cortex-M4 Instruction Set 62 Cortex-M4 Core Peripherals 209 Nested Vectored Interrupt Controller NVIC 210 System Control Block SCB 220 System Timer SysTick 246 Memory Protection Unit MPU 252 Floating Point Unit FPU 275 Glossary 284

Debug and Test Features 289

Description 289 Embedded Characteristics 289 Application Examples 290 Debug and Test Pin Description 291 Functional Description 292

Reset Controller RSTC 297

Description 297 Embedded Characteristics 297 Block Diagram. 297 Functional Description 298 Reset Controller RSTC User Interface 305
Ordering Information 858

Table of Contents i

SAM G51 [DATASHEET]

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Datasheet ID: ATSAMG51N18A-AU 519370