PCX8240VTPU200EZD3

PCX8240VTPU200EZD3 Datasheet

The letter X in the part number designates a "Prototype" product that has not been qualified by e2v. Reliability of a PCX partnumber is not guaranteed and such part-number shall not be used in Flight Hardware. Product changes may still occur while shipping prototypes.

Part	Datasheet
PCX8240VTPU200EZD3	PCX8240VTPU200EZD3 (pdf)

Related Parts	Information
PCX8240VTPU200E	PCX8240VTPU200E

PDF Datasheet Preview
PC8240 Integrated Processor Family Datasheet - Preliminary Specification • SPEC int 95, SPECfp95 at 266 MHz Estimated • Superscalar 603e Core • Integer Unit IU , Floating-Point Unit FPU User Enabled or Disabled , Load/Store Unit LSU , System Register Unit SRU , and a Branch Processing Unit BPU • 16-Kbyte Instruction Cache • 16-Kbyte Data Cache • Lockable L1 Caches - Entire Cache or on a Per-way Basis up to 3 of 4 Ways • Dynamic Power Management • High-bandwidth Bus 32/64 bits Data Bus to DRAM • Supports 1-Mbyte to 1-Gbyte DRAM Memory • 32-bit PCI Interface Operating up to 66 MHz • PCI 2.1-compliant, 5.0V Tolerance • Fint Max = 200 MHz • FBus Max = 66 MHz The PC8240 combines a Power Architecture 603e core microprocessor with a PCI bridge. The PC8240’s PCI support will allow system designers to rapidly design systems using peripherals already designed for PCI and the other standard interfaces. The PC8240 also integrates a highperformance memory controller which supports various types of DRAM and ROM. The PC8240 is the first of a family of products that provides system level support for industry standard interfaces with a Power Architecture microprocessor core. The peripheral logic integrates a PCI bridge, memory controller, DMA controller, EPIC interrupt controller, I2O controller, and a two-wire interface controller. The 603e core is a full-featured, high-performance processor with floating-point support, memory management, 16-Kbyte instruction cache, 16-Kbyte data cache, and power management features. The integration reduces the overall packaging requirements and the number of discrete devices required for an embedded system. The PC8240 contains an internal peripheral logic bus that interfaces the 603e core to the peripheral logic. The core can operate at a variety of frequencies, allowing the designer to trade off performance for power consumption. The 603e core is clocked from a separate PLL, which is referenced to the peripheral logic PLL. This allows the microprocessor and the peripheral logic block to operate at different frequencies, while maintaining a synchronous bus interface. The interface uses a 64- or 32-bit data bus depending on memory data bus width and a 32-bit address bus along with control signals that enable the interface between the processor and peripheral logic to be optimized for performance. PCI accesses to the PC8240’s memory space are passed to the processor bus for snooping purposes when snoop mode is enabled. e2v semiconductors SAS 2009 Visit our website for the latest version of the datasheet PC8240 [Preliminary] The PC8240’s features serve a variety of embedded applications. In this way, the 603e core and peripheral logic remain general-purpose. The PC8240 can be used as either a PCI host or an agent controller. Screening/Quality/Packaging This product is manufactured in full compliance with • Upscreening based upon e2v standards • Industrial temperature range Tc = Tc = +110° C Tc = Tc = +125° C ZD3 suffix • Core power supply ± 5 % V L-Spec for 200 MHz • I/O power supply 3.0V to 3.6V • 352 Tape Ball Grid Array TBGA TP suffix TBGA352 Tape Ball Grid Array e2v semiconductors SAS 2009 PC8240 [Preliminary] Block Diagram The PC8240 integrated processor is comprised of a peripheral logic block and a 32-bit superscalar Power Architecture 603e core, as shown in Figure Figure Block Diagram PC8240 603e Processor Core Block 64-bit Two-instruction fetch Additional features • JTAG/COP interface • Power management Processor PLL Branch Processing Unit BPU Instruction Unit 64-bit Two-instruction dispatch System Register Unit SRU Integer Unit IU Load/Store Unit LSU Data MMU 16-Kbyte Data Cache Floating Point Unit FPU 64-bit Instruction MMU 16-Kbyte Instruction Cache 5 IRQs/ 16 Serial Interrupts Peripheral Logic Bus This section provides the AC electrical characteristics for the PC8240. After fabrication, functional parts are sorted by maximum processor core frequency as shown in Table 4-4, “Clock AC Timing Specifications,” on page 20 and tested for conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus PCI_SYNC_IN clock frequency and the settings of the PLL_CFG[0-4] signals. Parts are sold by maximum processor core frequency see “Ordering Information” on page Table 4-3 provides the operating frequency information for the PC8240. At recommended operating conditions see Table 3-2 on page 9 with GVdd = 3.3V ± 5% and LVdd = 3.3V ± 5% Table Operating frequency Characteristic 1 200 MHz Processor Frequency CPU Memory Bus Frequency 25 - 100 PCI Input Frequency 25 - 66 Unit MHz Note: Caution The PCI_SYNC_IN frequency and PLL_CFG[0 4] settings must be chosen such that the resulting peripheral logic/memory bus frequency, CPU core frequency, and PLL VCO frequencies do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0 4] signal description in “PLL Configuration” on page 36 for valid PLL_CFG[0 4] settings and PCI_SYNC_IN frequencies. e2v semiconductors SAS 2009 PC8240 [Preliminary] Clock AC Specifications Table 4-4 provides the clock AC timing specifications as defined in Section. At recommended operating conditions see Table 3-2 on page 9 with GVdd = 3.3V ± 5% and LVdd = 3.3V ± 5% Table Clock AC Timing Specifications Num Characteristics and Conditions 1 1a Frequency of Operation PCI_SYNC_IN 1b PCI_SYNC_IN Cycle Time 2, 3 PCI_SYNC_IN Rise and Fall Times PCI_SYNC_IN Duty Cycle Measured at 1.4V 5a PCI_SYNC_IN Pulse Width High Measured at 1.4V 5b PCI_SYNC_IN Pulse Width Low Measured at 1.4V PCI_SYNC_IN Short Term Jitter Cycle to Cycle 8a PCI_CLK[0 4] Skew Pin to Pin 8b SDRAM_CLK[0 3] Skew Pin to Pin 10 Internal PLL Relock Time 15 DLL Lock Range with DLL_EXTEND = 0 disabled Default 16 DLL Lock Range with DLL_EXTEND = 1 enabled 17 Frequency of Operation OSC_IN 18 OSC_IN Cycle Time 19 OSC_IN Rise and Fall Times 20 OSC_IN Duty Cycle Measured at 1.4V 21 OSC_IN Frequency Stability OSC_IN VIH Loaded OSC_IN VIL Loaded < 500 0 NTclk - tloop - tfix0 7 Ordering Information xx 8240 Product Part Code 1 Identifier Temperature Range TC 1 Package 1 Screening Level 1 Max Internal Processor Speed 1 PC X 2 8240 V TP TBGA U Upscreening 200 MHz E TC = to For availability of the different versions, contact your local e2v sales office. The letter X in the part number designates a "Prototype" product that has not been qualified by e2v. Reliability of a PCX partnumber is not guaranteed and such part-number shall not be used in Flight Hardware. Product changes may still occur while shipping prototypes. Date 07/2007 Substantive Change s Name change from Atmel to e2v Ordering information update e2v semiconductors SAS 2009 PC8240 [Preliminary] Table of Contents 1 Description 1 Screening/Quality/Packaging 2 1 General Description 3 Block Diagram 3 Pinout Listing 4 2 Detailed Specification 8 3 Applicable Documents 8 Design and Construction 8 Absolute Maximum Ratings 8 Recommended Operating Conditions 9 Thermal Information Power Consideration 16 Marking 17 4 Electrical Characteristics 17 Static Characteristics 17 Dynamic Electrical Characteristics 19 5 Preparation for Delivery 34 Packaging 34 Certificate of Compliance 34 6 Handling 34 7 Package Description 34 Package Parameters 34 Mechanical Dimensions 35 PLL Configuration 36 System Design Information 37 8 Definitions 42 Life Support Applications 42 e2v semiconductors SAS 2009 How to reach us Home page: Sales offices: Europe Regional sales office e2v ltd 106 Waterhouse Lane Chelmsford Essex CM1 2QU England Tel +44 0 1245 493493 Fax +44 0 1245 492492 mailto: e2v sas 16 Burospace F-91572 Bièvres Cedex France Tel +33 0 16019 5500 Fax +33 0 16019 5529 mailto: e2v gmbh Industriestraße 29 82194 Gröbenzell Germany Tel +49 0 8142 41057-0 Fax +49 0 8142 284547 mailto: Americas e2v inc 520 White Plains Road Suite 450 Tarrytown, NY 10591 USA Tel +1 914 592 6050 or 1-800-342-5338, Fax +1 914 592-5148 mailto: Asia Pacific e2v ltd 11/F., Onfem Tower, 29 Wyndham Street, Central, Hong Kong Tel +852 3679 364 8/9 Fax +852 3583 1084 mailto: Product Contact e2v Avenue de Rochepleine BP 123 - 38521 Saint-Egrève Cedex France Tel +33 0 4 76 58 30 00 Hotline mailto: Whilst e2v has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. e2v accepts no liability beyond that set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein. e2v semiconductors SAS 2009

PDF Datasheet Preview

PC8240

Integrated Processor Family

Datasheet - Preliminary Specification
• SPEC int 95, SPECfp95 at 266 MHz Estimated
• Superscalar 603e Core
• Integer Unit IU , Floating-Point Unit FPU User Enabled or Disabled , Load/Store Unit LSU , System Register Unit SRU ,
and a Branch Processing Unit BPU
• 16-Kbyte Instruction Cache
• 16-Kbyte Data Cache
• Lockable L1 Caches - Entire Cache or on a Per-way Basis up to 3 of 4 Ways
• Dynamic Power Management
• High-bandwidth Bus 32/64 bits Data Bus to DRAM
• Supports 1-Mbyte to 1-Gbyte DRAM Memory
• 32-bit PCI Interface Operating up to 66 MHz
• PCI 2.1-compliant, 5.0V Tolerance
• Fint Max = 200 MHz
• FBus Max = 66 MHz

The PC8240 combines a Power Architecture 603e core microprocessor with a PCI bridge. The PC8240’s PCI support will allow system designers to rapidly design systems using peripherals already designed for PCI and the other standard interfaces. The PC8240 also integrates a highperformance memory controller which supports various types of DRAM and ROM. The PC8240 is the first of a family of products that provides system level support for industry standard interfaces with a Power Architecture microprocessor core.

The peripheral logic integrates a PCI bridge, memory controller, DMA controller, EPIC interrupt controller, I2O controller, and a two-wire interface controller. The 603e core is a full-featured, high-performance processor with floating-point support, memory management, 16-Kbyte instruction cache, 16-Kbyte data cache, and power management features. The integration reduces the overall packaging requirements and the number of discrete devices required for an embedded system.

The PC8240 contains an internal peripheral logic bus that interfaces the 603e core to the peripheral logic. The core can operate at a variety of frequencies, allowing the designer to trade off performance for power consumption. The 603e core is clocked from a separate PLL, which is referenced to the peripheral logic PLL. This allows the microprocessor and the peripheral logic block to operate at different frequencies, while maintaining a synchronous bus interface. The interface uses a 64- or 32-bit data bus depending on memory data bus width and a 32-bit address bus along with control signals that enable the interface between the processor and peripheral logic to be optimized for performance. PCI accesses to the PC8240’s memory space are passed to the processor bus for snooping purposes when snoop mode is enabled.
e2v semiconductors SAS 2009

Visit our website for the latest version of the datasheet

PC8240 [Preliminary]

The PC8240’s features serve a variety of embedded applications. In this way, the 603e core and peripheral logic remain general-purpose. The PC8240 can be used as either a PCI host or an agent controller.

Screening/Quality/Packaging

This product is manufactured in full compliance with
• Upscreening based upon e2v standards
• Industrial temperature range Tc = Tc = +110° C Tc = Tc = +125° C ZD3 suffix
• Core power supply ± 5 % V L-Spec for 200 MHz
• I/O power supply 3.0V to 3.6V
• 352 Tape Ball Grid Array TBGA

TP suffix TBGA352 Tape Ball Grid Array
e2v semiconductors SAS 2009

PC8240 [Preliminary]

Block Diagram

The PC8240 integrated processor is comprised of a peripheral logic block and a 32-bit superscalar Power Architecture 603e core, as shown in Figure

Figure Block Diagram

PC8240
603e Processor Core Block
64-bit Two-instruction fetch

Additional features
• JTAG/COP interface
• Power management

Processor PLL

Branch Processing

Unit BPU

Instruction Unit 64-bit Two-instruction dispatch

System Register

Unit SRU

Integer Unit IU

Load/Store Unit LSU

Data MMU
16-Kbyte Data Cache

Floating Point Unit FPU
64-bit

Instruction MMU
16-Kbyte Instruction

Cache
5 IRQs/ 16 Serial Interrupts

Peripheral Logic Bus
This section provides the AC electrical characteristics for the PC8240. After fabrication, functional parts are sorted by maximum processor core frequency as shown in Table 4-4, “Clock AC Timing Specifications,” on page 20 and tested for conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus PCI_SYNC_IN clock frequency and the settings of the PLL_CFG[0-4] signals. Parts are sold by maximum processor core frequency see “Ordering Information” on page

Table 4-3 provides the operating frequency information for the PC8240.

At recommended operating conditions see Table 3-2 on page 9 with GVdd = 3.3V ± 5% and LVdd = 3.3V ± 5%

Table Operating frequency

Characteristic 1
200 MHz

Processor Frequency CPU

Memory Bus Frequency
25 - 100

PCI Input Frequency
25 - 66

Unit MHz

Note:

Caution The PCI_SYNC_IN frequency and PLL_CFG[0 4] settings must be chosen such that the resulting peripheral logic/memory bus frequency, CPU core frequency, and PLL VCO frequencies do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0 4] signal description in “PLL Configuration” on page 36 for valid PLL_CFG[0 4] settings and PCI_SYNC_IN frequencies.
e2v semiconductors SAS 2009

PC8240 [Preliminary]

Clock AC Specifications Table 4-4 provides the clock AC timing specifications as defined in Section.

At recommended operating conditions see Table 3-2 on page 9 with GVdd = 3.3V ± 5% and LVdd = 3.3V ± 5%

Table Clock AC Timing Specifications

Num Characteristics and Conditions 1
1a Frequency of Operation PCI_SYNC_IN
1b PCI_SYNC_IN Cycle Time
2, 3 PCI_SYNC_IN Rise and Fall Times

PCI_SYNC_IN Duty Cycle Measured at 1.4V
5a PCI_SYNC_IN Pulse Width High Measured at 1.4V
5b PCI_SYNC_IN Pulse Width Low Measured at 1.4V

PCI_SYNC_IN Short Term Jitter Cycle to Cycle
8a PCI_CLK[0 4] Skew Pin to Pin
8b SDRAM_CLK[0 3] Skew Pin to Pin
10 Internal PLL Relock Time
15 DLL Lock Range with DLL_EXTEND = 0 disabled Default
16 DLL Lock Range with DLL_EXTEND = 1 enabled
17 Frequency of Operation OSC_IN
18 OSC_IN Cycle Time
19 OSC_IN Rise and Fall Times
20 OSC_IN Duty Cycle Measured at 1.4V
21 OSC_IN Frequency Stability

OSC_IN VIH Loaded

OSC_IN VIL Loaded
< 500
0 NTclk - tloop - tfix0 7
Ordering Information
xx 8240

Product

Part

Code 1 Identifier

Temperature Range TC 1

Package 1

Screening Level 1

Max Internal Processor Speed 1

PC X 2
8240 V TP TBGA U Upscreening
200 MHz

E TC = to

For availability of the different versions, contact your local e2v sales office.

The letter X in the part number designates a "Prototype" product that has not been qualified by e2v. Reliability of a PCX partnumber is not guaranteed and such part-number shall not be used in Flight Hardware. Product changes may still occur while shipping prototypes.

Date 07/2007

Substantive Change s
Name change from Atmel to e2v Ordering information update
e2v semiconductors SAS 2009

PC8240 [Preliminary]

Table of Contents
1 Description 1 Screening/Quality/Packaging 2 1 General Description 3

Block Diagram 3 Pinout Listing 4
2 Detailed Specification 8 3 Applicable Documents 8

Design and Construction 8 Absolute Maximum Ratings 8 Recommended Operating Conditions 9 Thermal Information Power Consideration 16 Marking 17
4 Electrical Characteristics 17

Static Characteristics 17 Dynamic Electrical Characteristics 19
5 Preparation for Delivery 34

Packaging 34 Certificate of Compliance 34
6 Handling 34 7 Package Description 34

Package Parameters 34 Mechanical Dimensions 35 PLL Configuration 36 System Design Information 37
8 Definitions 42

Life Support Applications 42
e2v semiconductors SAS 2009

How to reach us

Home page:

Sales offices:

Europe Regional sales office e2v ltd 106 Waterhouse Lane Chelmsford Essex CM1 2QU England Tel +44 0 1245 493493 Fax +44 0 1245 492492 mailto:
e2v sas 16 Burospace F-91572 Bièvres Cedex France Tel +33 0 16019 5500 Fax +33 0 16019 5529 mailto:
e2v gmbh Industriestraße 29 82194 Gröbenzell Germany Tel +49 0 8142 41057-0 Fax +49 0 8142 284547 mailto:

Americas e2v inc 520 White Plains Road Suite 450 Tarrytown, NY 10591 USA Tel +1 914 592 6050 or 1-800-342-5338, Fax +1 914 592-5148 mailto:

Asia Pacific e2v ltd 11/F., Onfem Tower, 29 Wyndham Street, Central, Hong Kong Tel +852 3679 364 8/9 Fax +852 3583 1084 mailto:

Product Contact e2v Avenue de Rochepleine BP 123 - 38521 Saint-Egrève Cedex France Tel +33 0 4 76 58 30 00 Hotline mailto:

Whilst e2v has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. e2v accepts no liability beyond that set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein.
e2v semiconductors SAS 2009

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived PCX8240VTPU200EZD3 Datasheet file may be downloaded here without warranties.

Datasheet ID: PCX8240VTPU200EZD3 519352